PORTO @ Archivio Istituzionale della Ricerca

BERNARDI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 16.879
NA - Nord America 15.998
AS - Asia 3.061
AF - Africa 78
SA - Sud America 70
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 7
Totale 36.101
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Nazione #
US - Stati Uniti d'America 15.828
IT - Italia 4.069
GB - Regno Unito 3.559
FR - Francia 2.871
DE - Germania 2.617
CN - Cina 1.246
UA - Ucraina 875
RU - Federazione Russa 853
SG - Singapore 585
TR - Turchia 438
NL - Olanda 377
IE - Irlanda 335
SE - Svezia 306
KR - Corea 282
CH - Svizzera 231
CA - Canada 170
FI - Finlandia 169
JO - Giordania 129
IN - India 127
AT - Austria 125
BE - Belgio 116
JP - Giappone 87
HK - Hong Kong 57
EU - Europa 53
SN - Senegal 45
RO - Romania 40
BR - Brasile 35
ID - Indonesia 34
PL - Polonia 33
EE - Estonia 28
IL - Israele 25
TW - Taiwan 24
BG - Bulgaria 22
GR - Grecia 21
IR - Iran 20
CZ - Repubblica Ceca 18
PT - Portogallo 18
ES - Italia 17
CL - Cile 16
AP - ???statistics.table.value.countryCode.AP??? 15
LT - Lituania 13
MY - Malesia 13
TH - Thailandia 10
AE - Emirati Arabi Uniti 9
DZ - Algeria 9
UY - Uruguay 9
AU - Australia 8
DK - Danimarca 8
EG - Egitto 8
HR - Croazia 8
CO - Colombia 6
LU - Lussemburgo 6
NO - Norvegia 6
NG - Nigeria 5
PK - Pakistan 5
SK - Slovacchia (Repubblica Slovacca) 5
VN - Vietnam 5
BY - Bielorussia 4
AL - Albania 3
CY - Cipro 3
HU - Ungheria 3
MA - Marocco 3
MD - Moldavia 3
MO - Macao, regione amministrativa speciale della Cina 3
PE - Perù 3
SA - Arabia Saudita 3
AM - Armenia 2
ET - Etiopia 2
KZ - Kazakistan 2
PH - Filippine 2
RS - Serbia 2
SC - Seychelles 2
SI - Slovenia 2
AR - Argentina 1
AZ - Azerbaigian 1
GH - Ghana 1
IQ - Iraq 1
MM - Myanmar 1
NE - Niger 1
NP - Nepal 1
TN - Tunisia 1
UZ - Uzbekistan 1
ZW - Zimbabwe 1
Totale 36.101
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Città #
Ashburn 4.381
Southend 3.266
Seattle 1.842
Fairfield 1.273
Turin 952
Chandler 814
Woodbridge 625
Princeton 500
Houston 499
Ann Arbor 460
Torino 438
Wilmington 432
Jacksonville 431
Boardman 430
Cambridge 418
Singapore 397
Dublin 318
Berlin 294
Milan 270
Beijing 267
Izmir 255
San Ramon 249
Saint Petersburg 235
Hangzhou 230
Bologna 227
Bern 210
Council Bluffs 208
San Donato Milanese 163
Chicago 162
Shanghai 153
Helsinki 151
Zhengzhou 144
Zaporozhye 115
Istanbul 112
Vienna 112
Des Moines 111
Brussels 107
Mountain View 107
Baltimore 98
Pennsylvania Furnace 97
Santa Clara 96
Overberg 87
Monopoli 84
Padua 69
Waterloo 68
Amsterdam 67
San Diego 66
Dearborn 57
Malatya 57
Rome 57
Rotterdam 57
Aubervilliers 52
Toronto 50
Paris 49
Bremen 48
Redwood City 48
New York 47
Shenzhen 45
Duncan 40
Frankfurt 40
Buffalo 38
London 37
Guangzhou 36
Penza 36
San Francisco 35
Seoul 35
Fremont 32
Las Vegas 31
Neubiberg 31
Ottawa 30
Washington 28
Herkenbosch 27
Munich 27
Melun 26
Miami 26
St Petersburg 25
Jakarta 24
Falls Church 23
Moscow 23
Frankfurt am Main 22
Kraków 22
Norwalk 22
Stuttgart 22
Sofia 21
Tallinn 20
Varese 20
Yubileyny 20
Porto Alegre 19
Andover 18
Chengdu 17
Collegno 17
Piscataway 17
San Jose 17
Hefei 16
Kiev 16
Modena 16
Studio City 16
Palermo 15
Podenzano 15
Fuzhou 14
Totale 23.689
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Nome #
Agri-Food Traceability Management using a RFID System with Privacy Protection 625
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 497
A SBST strategy to test microprocessors' branch target buffer 430
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors 429
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers 412
Peak Power Estimation: A Case Study on CPU Cores 411
On-line functionally untestable fault identification in embedded processor cores 404
An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs 383
On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors 383
An effective approach to automatic functional processor test generation for small-delay faults 378
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains 361
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-line Self-Test 359
Software-based self-test techniques of computational modules in dual issue embedded processors 356
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs 345
An Effective Methodology for On-line Testing of Embedded Microprocessors 342
On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors 339
A new hybrid fault detection technique for systems-on-a-chip 329
A Parallel Tester Architecture for Accelerometerand Gyroscope MEMS Calibration and Test 329
Software-based self-test of embedded microprocessors 328
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs 326
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores 325
Design of an UHF RFID Transponder for Secure Authentication 325
Integrating BIST techniques for on-line SoC testing 321
An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices 321
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors 321
An efficient method for the test of embedded memory cores during the operational phase 315
An adaptive low-cost tester architecture supporting embedded memory volume diagnosis 313
Identification and classification of single-event upsets in the configuration memory of sram-based fpgas 312
An Optimized Test During Burn-In for Automotive SoC 311
A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC 311
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller 306
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques 301
SW-Based Transparent In-Field Memory Testing 299
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 298
Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems 293
Embedded Memory Diagnosis: An Industrial Workflow 286
An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores 284
A Hybrid Approach to Fault Detection and Correction in SoCs 283
System-in-package testing: problems and solutions 280
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core 279
A new Architecture to Cross-Fertilize On-line and Manufacturing Testing 279
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs 277
A Programmable BIST for DRAM Testing and Diagnosis 276
On the automation of the test flow of complex SoCs 275
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In 275
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis 274
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores 271
A System-layer Infrastructure for SoC Diagnosis 271
Diagnosing faulty functional units in processors by using automatically generated test sets 270
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 267
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test 267
A fault grading methodology for software-based self-test programs in systems-on-chip 266
Extended Fault Detection Techniques for Systems-on-Chip 266
Test, Reliability and Functional Safety trends for Automotive System-on-Chip 266
A P1500-compatible programmable BIST approach for the test of embedded flash memories 265
Microprocessor Testing: Functional Meets Structural Test 264
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug 262
On the evaluation of SEU sensitiveness in SRAM-based FPGAs 260
Test Techniques for System-on-Chip: Problems and solutions 259
Using Infrastructure IPs to support SW-based Self-Test of Processor Cores 258
An optimized hybrid approach to provide fault detection and correction in SoCs 258
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications 256
Thermal issues in test: An overview of the significant aspects and industrial practice 255
Testing logic cores using a BIST P1500 compliant approach: a case of study 255
A pattern ordering algorithm for reducing the size of fault dictionaries 254
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm 254
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers 254
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption 254
A tester architecture suitable for MEMS calibration and testing 252
In-field functional test programs development flow for embedded FPUs 252
An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization 252
Fault grading of software-based self-test procedures for dependable automotive applications 251
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing 250
An effective ATPG flow for Gate Delay Faults 249
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization 248
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs 247
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study 247
Optimized embedded memory diagnosis 246
Scan-Chain Intra-Cell Aware Testing 245
Exploiting an I-IP for both test and silicon debug of microprocessor cores 244
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC 243
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA 243
An Exact and Efficient Critical Path Tracing Algorithm 242
Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS) 242
An integrated approach for increasing the soft-error detection capabilities in SoCs processors 242
An effective approach for functional test programs compaction 241
Test Considerations about the Structured ASIC Paradigm 241
Evaluating Alpha-induced Soft Errors in Embedded Microprocessors 236
Exploiting an I-IP for In-field SOC test 235
Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC 233
An adaptive tester architecture for volume diagnosis 231
An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs 230
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores 227
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults 224
SoC Symbolic Simulation: a case study on delay fault testing 224
An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives 223
Faster-than-at-speed execution of functional programs: an experimental analysis 222
A new DFM-proactive technique 220
A Tool for Supporting and Automating the Test of Complex System-on-Chips 217
Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs 216
Totale 28.873
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Categoria #
all - tutte 99.539
article - articoli 18.688
book - libri 756
conference - conferenze 77.476
curatela - curatele 0
other - altro 360
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.259
Totale 199.078
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.527 0 0 0 0 474 417 301 471 423 202 139 100
2020/20212.660 326 428 129 341 124 206 184 211 146 257 189 119
2021/20221.891 115 137 46 49 133 123 84 117 74 146 391 476
2022/20233.296 236 489 180 248 307 436 279 156 415 30 164 356
2023/20241.359 115 139 83 99 156 219 69 91 37 49 126 176
2024/20252.077 129 785 210 762 191 0 0 0 0 0 0 0
Totale 36.330