BERNARDI, PAOLO
 Distribuzione geografica
Continente #
EU - Europa 16.461
NA - Nord America 15.126
AS - Asia 2.202
AF - Africa 77
SA - Sud America 70
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 7
Totale 33.951
Nazione #
US - Stati Uniti d'America 14.970
IT - Italia 3.935
GB - Regno Unito 3.543
FR - Francia 2.842
DE - Germania 2.601
CN - Cina 1.036
UA - Ucraina 869
RU - Federazione Russa 719
NL - Olanda 371
IE - Irlanda 331
TR - Turchia 325
SE - Svezia 306
CH - Svizzera 231
KR - Corea 206
FI - Finlandia 159
CA - Canada 156
SG - Singapore 152
JO - Giordania 129
IN - India 126
AT - Austria 122
JP - Giappone 87
BE - Belgio 76
EU - Europa 53
HK - Hong Kong 53
SN - Senegal 45
RO - Romania 37
BR - Brasile 35
PL - Polonia 32
EE - Estonia 28
IL - Israele 25
TW - Taiwan 23
BG - Bulgaria 21
GR - Grecia 21
IR - Iran 20
PT - Portogallo 18
CL - Cile 16
AP - ???statistics.table.value.countryCode.AP??? 15
CZ - Repubblica Ceca 15
ES - Italia 15
ID - Indonesia 14
MY - Malesia 13
TH - Thailandia 10
DZ - Algeria 9
UY - Uruguay 9
AE - Emirati Arabi Uniti 8
AU - Australia 8
DK - Danimarca 8
HR - Croazia 8
EG - Egitto 7
CO - Colombia 6
LU - Lussemburgo 6
NG - Nigeria 5
NO - Norvegia 5
PK - Pakistan 5
SK - Slovacchia (Repubblica Slovacca) 5
VN - Vietnam 5
BY - Bielorussia 4
LT - Lituania 4
AL - Albania 3
CY - Cipro 3
HU - Ungheria 3
MA - Marocco 3
MD - Moldavia 3
MO - Macao, regione amministrativa speciale della Cina 3
PE - Perù 3
SA - Arabia Saudita 3
AM - Armenia 2
ET - Etiopia 2
KZ - Kazakistan 2
PH - Filippine 2
RS - Serbia 2
SC - Seychelles 2
SI - Slovenia 2
AR - Argentina 1
AZ - Azerbaigian 1
GH - Ghana 1
IQ - Iraq 1
MM - Myanmar 1
NE - Niger 1
NP - Nepal 1
TN - Tunisia 1
UZ - Uzbekistan 1
ZW - Zimbabwe 1
Totale 33.951
Città #
Ashburn 4.368
Southend 3.266
Seattle 1.842
Fairfield 1.273
Turin 890
Chandler 814
Woodbridge 625
Princeton 500
Houston 499
Ann Arbor 460
Torino 438
Wilmington 432
Jacksonville 431
Cambridge 418
Dublin 314
Berlin 294
Boardman 268
Beijing 267
Izmir 252
Milan 250
San Ramon 249
Saint Petersburg 235
Hangzhou 230
Bologna 227
Bern 210
Council Bluffs 192
San Donato Milanese 163
Chicago 162
Shanghai 152
Helsinki 146
Zhengzhou 144
Zaporozhye 115
Des Moines 111
Vienna 110
Mountain View 107
Baltimore 98
Pennsylvania Furnace 97
Overberg 87
Monopoli 84
Singapore 78
Padua 69
Waterloo 68
Brussels 67
San Diego 64
Amsterdam 61
Dearborn 57
Malatya 57
Rotterdam 57
Rome 55
Aubervilliers 52
Bremen 48
Redwood City 48
Shenzhen 45
Duncan 40
Frankfurt 40
Toronto 40
Buffalo 38
New York 37
Guangzhou 36
Penza 36
Seoul 35
San Francisco 33
Fremont 32
Las Vegas 31
Neubiberg 31
London 30
Paris 28
Washington 28
Herkenbosch 27
Melun 26
Miami 26
Ottawa 26
Munich 25
St Petersburg 25
Falls Church 23
Kraków 22
Norwalk 22
Stuttgart 22
Sofia 21
Moscow 20
Tallinn 20
Varese 20
Porto Alegre 19
Andover 18
Chengdu 17
Collegno 17
San Jose 17
Hefei 16
Kiev 16
Modena 16
Studio City 16
Palermo 15
Podenzano 15
Frankfurt am Main 14
Nanjing 14
San Antonio 14
Perugia 13
Atlanta 12
Bangalore 12
Fuzhou 12
Totale 22.759
Nome #
Agri-Food Traceability Management using a RFID System with Privacy Protection 577
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 486
A SBST strategy to test microprocessors' branch target buffer 420
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors 417
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers 395
Peak Power Estimation: A Case Study on CPU Cores 394
On-line functionally untestable fault identification in embedded processor cores 391
An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs 371
On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors 371
An effective approach to automatic functional processor test generation for small-delay faults 366
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains 349
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-line Self-Test 348
Software-based self-test techniques of computational modules in dual issue embedded processors 347
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs 333
An Effective Methodology for On-line Testing of Embedded Microprocessors 328
A new hybrid fault detection technique for systems-on-a-chip 321
On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors 321
A Parallel Tester Architecture for Accelerometerand Gyroscope MEMS Calibration and Test 319
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores 316
Software-based self-test of embedded microprocessors 315
Integrating BIST techniques for on-line SoC testing 313
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs 312
An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices 311
Design of an UHF RFID Transponder for Secure Authentication 310
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors 309
An efficient method for the test of embedded memory cores during the operational phase 302
An adaptive low-cost tester architecture supporting embedded memory volume diagnosis 301
Identification and classification of single-event upsets in the configuration memory of sram-based fpgas 300
A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC 295
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller 290
An Optimized Test During Burn-In for Automotive SoC 290
Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems 286
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 285
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques 283
SW-Based Transparent In-Field Memory Testing 281
Embedded Memory Diagnosis: An Industrial Workflow 279
System-in-package testing: problems and solutions 273
An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores 272
A Hybrid Approach to Fault Detection and Correction in SoCs 271
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs 270
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core 269
A Programmable BIST for DRAM Testing and Diagnosis 266
On the automation of the test flow of complex SoCs 266
Diagnosing faulty functional units in processors by using automatically generated test sets 265
A new Architecture to Cross-Fertilize On-line and Manufacturing Testing 265
A System-layer Infrastructure for SoC Diagnosis 263
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis 261
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores 261
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 259
A P1500-compatible programmable BIST approach for the test of embedded flash memories 257
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test 256
Extended Fault Detection Techniques for Systems-on-Chip 256
A fault grading methodology for software-based self-test programs in systems-on-chip 255
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In 254
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug 252
Using Infrastructure IPs to support SW-based Self-Test of Processor Cores 250
An optimized hybrid approach to provide fault detection and correction in SoCs 250
Microprocessor Testing: Functional Meets Structural Test 250
On the evaluation of SEU sensitiveness in SRAM-based FPGAs 250
Test Techniques for System-on-Chip: Problems and solutions 249
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications 248
A pattern ordering algorithm for reducing the size of fault dictionaries 246
Testing logic cores using a BIST P1500 compliant approach: a case of study 246
Test, Reliability and Functional Safety trends for Automotive System-on-Chip 244
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm 243
Fault grading of software-based self-test procedures for dependable automotive applications 243
In-field functional test programs development flow for embedded FPUs 242
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption 242
An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization 242
Thermal issues in test: An overview of the significant aspects and industrial practice 241
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization 241
A tester architecture suitable for MEMS calibration and testing 240
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers 240
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing 239
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA 238
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs 237
Exploiting an I-IP for both test and silicon debug of microprocessor cores 237
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC 236
An effective ATPG flow for Gate Delay Faults 236
Optimized embedded memory diagnosis 235
An integrated approach for increasing the soft-error detection capabilities in SoCs processors 235
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study 235
Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS) 233
An Exact and Efficient Critical Path Tracing Algorithm 232
Test Considerations about the Structured ASIC Paradigm 232
Scan-Chain Intra-Cell Aware Testing 231
Exploiting an I-IP for In-field SOC test 228
An effective approach for functional test programs compaction 226
Evaluating Alpha-induced Soft Errors in Embedded Microprocessors 225
An adaptive tester architecture for volume diagnosis 224
Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC 222
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores 220
An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs 217
SoC Symbolic Simulation: a case study on delay fault testing 215
A new DFM-proactive technique 212
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults 212
Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs 210
An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives 210
A Tool for Supporting and Automating the Test of Complex System-on-Chips 209
Scan-Chain Intra-Cell Defects Grading 205
Totale 27.721
Categoria #
all - tutte 90.237
article - articoli 16.810
book - libri 710
conference - conferenze 70.376
curatela - curatele 0
other - altro 295
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.046
Totale 180.474


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019657 0 0 0 0 0 0 0 0 0 0 0 657
2019/20203.753 368 237 111 510 474 417 301 471 423 202 139 100
2020/20212.660 326 428 129 341 124 206 184 211 146 257 189 119
2021/20221.891 115 137 46 49 133 123 84 117 74 146 391 476
2022/20233.296 236 489 180 248 307 436 279 156 415 30 164 356
2023/20241.261 115 139 83 99 156 219 69 91 37 49 126 78
Totale 34.155