BERNARDI, PAOLO
 Distribuzione geografica
Continente #
EU - Europa 15744
NA - Nord America 14348
AS - Asia 1928
AF - Africa 76
SA - Sud America 69
Continente sconosciuto - Info sul continente non disponibili 7
OC - Oceania 6
Totale 32178
Nazione #
US - Stati Uniti d'America 14195
IT - Italia 3691
GB - Regno Unito 3491
FR - Francia 2818
DE - Germania 2568
CN - Cina 962
UA - Ucraina 862
RU - Federazione Russa 691
NL - Olanda 340
TR - Turchia 323
IE - Irlanda 317
SE - Svezia 306
KR - Corea 200
CA - Canada 153
JO - Giordania 129
FI - Finlandia 122
IN - India 118
AT - Austria 117
JP - Giappone 81
EU - Europa 53
BE - Belgio 50
SN - Senegal 45
HK - Hong Kong 44
RO - Romania 37
BR - Brasile 35
PL - Polonia 32
EE - Estonia 28
IL - Israele 25
BG - Bulgaria 21
CH - Svizzera 21
GR - Grecia 20
IR - Iran 20
TW - Taiwan 20
PT - Portogallo 18
CL - Cile 16
AP - ???statistics.table.value.countryCode.AP??? 15
CZ - Repubblica Ceca 15
ES - Italia 15
MY - Malesia 13
DZ - Algeria 9
UY - Uruguay 9
AE - Emirati Arabi Uniti 8
DK - Danimarca 8
HR - Croazia 8
ID - Indonesia 8
AU - Australia 6
EG - Egitto 6
LU - Lussemburgo 6
CO - Colombia 5
NG - Nigeria 5
NO - Norvegia 5
PK - Pakistan 5
SK - Slovacchia (Repubblica Slovacca) 5
VN - Vietnam 5
BY - Bielorussia 4
TH - Thailandia 4
AL - Albania 3
CY - Cipro 3
MA - Marocco 3
MD - Moldavia 3
PE - Perù 3
SA - Arabia Saudita 3
AM - Armenia 2
ET - Etiopia 2
HU - Ungheria 2
KZ - Kazakistan 2
PH - Filippine 2
RS - Serbia 2
SC - Seychelles 2
SI - Slovenia 2
AR - Argentina 1
AZ - Azerbaigian 1
GH - Ghana 1
IQ - Iraq 1
MM - Myanmar 1
NE - Niger 1
NP - Nepal 1
SG - Singapore 1
TN - Tunisia 1
UZ - Uzbekistan 1
ZW - Zimbabwe 1
Totale 32178
Città #
Ashburn 4150
Southend 3266
Seattle 1822
Fairfield 1273
Chandler 814
Turin 763
Woodbridge 625
Princeton 500
Houston 499
Ann Arbor 460
Torino 438
Wilmington 432
Jacksonville 431
Cambridge 418
Dublin 301
Berlin 294
Izmir 252
San Ramon 249
Saint Petersburg 235
Beijing 232
Hangzhou 228
Bologna 227
Milan 212
Boardman 178
San Donato Milanese 163
Chicago 161
Zhengzhou 144
Shanghai 135
Helsinki 117
Zaporozhye 115
Des Moines 111
Vienna 110
Mountain View 107
Baltimore 98
Pennsylvania Furnace 97
Overberg 87
Monopoli 84
Padua 69
Waterloo 68
San Diego 64
Dearborn 57
Malatya 57
Rotterdam 57
Aubervilliers 52
Amsterdam 50
Bremen 48
Redwood City 48
Rome 46
Shenzhen 42
Brussels 41
Duncan 40
Frankfurt 40
Toronto 40
Buffalo 37
New York 37
Penza 36
Guangzhou 33
San Francisco 33
Fremont 32
Las Vegas 31
Neubiberg 31
Seoul 29
Herkenbosch 27
Melun 26
Ottawa 26
Paris 25
Falls Church 23
Kraków 22
Norwalk 22
Stuttgart 22
Sofia 21
Moscow 20
Munich 20
Tallinn 20
Varese 20
London 19
Porto Alegre 19
Andover 18
Chengdu 17
Collegno 17
Hefei 16
Kiev 16
Modena 16
San Jose 16
Studio City 16
Podenzano 15
Nanjing 14
San Antonio 14
Perugia 13
Atlanta 12
Bangalore 12
Fuzhou 12
Verona 12
Almese 11
Amarillo 11
Athens 11
Delft 11
Iasi 11
Tel Aviv 11
Frankfurt Am Main 10
Totale 21590
Nome #
Agri-Food Traceability Management using a RFID System with Privacy Protection 535
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 476
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors 413
A SBST strategy to test microprocessors' branch target buffer 405
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers 389
On-line functionally untestable fault identification in embedded processor cores 386
Peak Power Estimation: A Case Study on CPU Cores 383
On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors 365
An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs 364
An effective approach to automatic functional processor test generation for small-delay faults 360
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains 344
Software-based self-test techniques of computational modules in dual issue embedded processors 342
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-line Self-Test 341
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs 326
An Effective Methodology for On-line Testing of Embedded Microprocessors 322
On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors 319
A new hybrid fault detection technique for systems-on-a-chip 316
A Parallel Tester Architecture for Accelerometerand Gyroscope MEMS Calibration and Test 316
Software-based self-test of embedded microprocessors 311
Integrating BIST techniques for on-line SoC testing 306
Design of an UHF RFID Transponder for Secure Authentication 305
An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices 303
An efficient method for the test of embedded memory cores during the operational phase 297
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors 295
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs 293
An adaptive low-cost tester architecture supporting embedded memory volume diagnosis 292
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores 291
Identification and classification of single-event upsets in the configuration memory of sram-based fpgas 287
An Optimized Test During Burn-In for Automotive SoC 285
Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems 281
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 281
SW-Based Transparent In-Field Memory Testing 275
A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC 275
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller 272
Embedded Memory Diagnosis: An Industrial Workflow 270
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques 268
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core 267
System-in-package testing: problems and solutions 265
On the automation of the test flow of complex SoCs 264
A Programmable BIST for DRAM Testing and Diagnosis 263
A new Architecture to Cross-Fertilize On-line and Manufacturing Testing 262
An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores 261
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs 261
Diagnosing faulty functional units in processors by using automatically generated test sets 260
A Hybrid Approach to Fault Detection and Correction in SoCs 259
A System-layer Infrastructure for SoC Diagnosis 257
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 256
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis 256
A P1500-compatible programmable BIST approach for the test of embedded flash memories 252
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test 251
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores 251
Using Infrastructure IPs to support SW-based Self-Test of Processor Cores 247
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In 247
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug 246
On the evaluation of SEU sensitiveness in SRAM-based FPGAs 246
Microprocessor Testing: Functional Meets Structural Test 244
Extended Fault Detection Techniques for Systems-on-Chip 244
An optimized hybrid approach to provide fault detection and correction in SoCs 242
A pattern ordering algorithm for reducing the size of fault dictionaries 242
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications 242
Test Techniques for System-on-Chip: Problems and solutions 242
A fault grading methodology for software-based self-test programs in systems-on-chip 238
In-field functional test programs development flow for embedded FPUs 238
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption 237
Testing logic cores using a BIST P1500 compliant approach: a case of study 237
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm 236
Fault grading of software-based self-test procedures for dependable automotive applications 235
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers 234
Thermal issues in test: An overview of the significant aspects and industrial practice 233
A tester architecture suitable for MEMS calibration and testing 231
An effective ATPG flow for Gate Delay Faults 231
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization 231
An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization 231
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC 230
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs 228
Scan-Chain Intra-Cell Aware Testing 228
Optimized embedded memory diagnosis 227
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing 227
Test Considerations about the Structured ASIC Paradigm 227
An integrated approach for increasing the soft-error detection capabilities in SoCs processors 227
Exploiting an I-IP for both test and silicon debug of microprocessor cores 227
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study 227
An Exact and Efficient Critical Path Tracing Algorithm 226
Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS) 226
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA 226
Exploiting an I-IP for In-field SOC test 224
Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC 219
Evaluating Alpha-induced Soft Errors in Embedded Microprocessors 217
An effective approach for functional test programs compaction 217
An adaptive tester architecture for volume diagnosis 216
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores 212
An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs 211
A new DFM-proactive technique 206
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults 206
SoC Symbolic Simulation: a case study on delay fault testing 206
Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs 202
An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives 202
Scan-Chain Intra-Cell Defects Grading 201
A Tool for Supporting and Automating the Test of Complex System-on-Chips 200
Exploiting programmable BIST for the diagnosis of embedded memory cores 200
Totale 26893
Categoria #
all - tutte 68811
article - articoli 12769
book - libri 560
conference - conferenze 53741
curatela - curatele 0
other - altro 169
patent - brevetti 0
selected - selezionate 0
volume - volumi 1572
Totale 137622


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2017/20181250 0000 00 00 678126230216
2018/20193789 199183355416 33220 14826 221521810657
2019/20203753 368237111510 474417 301471 423202139100
2020/20212660 326428129341 124206 184211 146257189119
2021/20221891 1151374649 133123 84117 74146391476
2022/20232752 236489180248 307436 303164 389000
Totale 32350