PORTO @ Archivio Istituzionale della Ricerca

BERNARDI, PAOLO
 Distribuzione geografica
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Continente #
EU - Europa 16.570
NA - Nord America 15.636
AS - Asia 2.758
AF - Africa 77
SA - Sud America 70
OC - Oceania 8
Continente sconosciuto - Info sul continente non disponibili 7
Totale 35.126
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Nazione #
US - Stati Uniti d'America 15.480
IT - Italia 3.991
GB - Regno Unito 3.544
FR - Francia 2.849
DE - Germania 2.606
CN - Cina 1.217
UA - Ucraina 873
RU - Federazione Russa 722
SG - Singapore 485
NL - Olanda 374
IE - Irlanda 334
TR - Turchia 328
SE - Svezia 306
KR - Corea 241
CH - Svizzera 231
FI - Finlandia 163
CA - Canada 156
JO - Giordania 129
IN - India 126
AT - Austria 124
BE - Belgio 94
JP - Giappone 87
HK - Hong Kong 56
EU - Europa 53
SN - Senegal 45
RO - Romania 37
BR - Brasile 35
PL - Polonia 32
EE - Estonia 28
IL - Israele 25
TW - Taiwan 24
BG - Bulgaria 22
GR - Grecia 21
IR - Iran 20
PT - Portogallo 18
ES - Italia 17
CL - Cile 16
AP - ???statistics.table.value.countryCode.AP??? 15
CZ - Repubblica Ceca 15
ID - Indonesia 14
MY - Malesia 13
TH - Thailandia 10
DZ - Algeria 9
UY - Uruguay 9
AE - Emirati Arabi Uniti 8
AU - Australia 8
DK - Danimarca 8
HR - Croazia 8
EG - Egitto 7
CO - Colombia 6
LU - Lussemburgo 6
NG - Nigeria 5
NO - Norvegia 5
PK - Pakistan 5
SK - Slovacchia (Repubblica Slovacca) 5
VN - Vietnam 5
BY - Bielorussia 4
LT - Lituania 4
AL - Albania 3
CY - Cipro 3
HU - Ungheria 3
MA - Marocco 3
MD - Moldavia 3
MO - Macao, regione amministrativa speciale della Cina 3
PE - Perù 3
SA - Arabia Saudita 3
AM - Armenia 2
ET - Etiopia 2
KZ - Kazakistan 2
PH - Filippine 2
RS - Serbia 2
SC - Seychelles 2
SI - Slovenia 2
AR - Argentina 1
AZ - Azerbaigian 1
GH - Ghana 1
IQ - Iraq 1
MM - Myanmar 1
NE - Niger 1
NP - Nepal 1
TN - Tunisia 1
UZ - Uzbekistan 1
ZW - Zimbabwe 1
Totale 35.126
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Città #
Ashburn 4.377
Southend 3.266
Seattle 1.842
Fairfield 1.273
Turin 914
Chandler 814
Woodbridge 625
Princeton 500
Houston 499
Ann Arbor 460
Torino 438
Wilmington 432
Jacksonville 431
Boardman 430
Cambridge 418
Singapore 322
Dublin 317
Berlin 294
Beijing 267
Milan 260
Izmir 255
San Ramon 249
Saint Petersburg 235
Hangzhou 230
Bologna 227
Bern 210
Council Bluffs 208
San Donato Milanese 163
Chicago 162
Shanghai 153
Helsinki 147
Zhengzhou 144
Zaporozhye 115
Des Moines 111
Vienna 111
Mountain View 107
Baltimore 98
Pennsylvania Furnace 97
Overberg 87
Brussels 85
Monopoli 84
Padua 69
Waterloo 68
Amsterdam 64
San Diego 64
Dearborn 57
Malatya 57
Rotterdam 57
Rome 55
Aubervilliers 52
Bremen 48
Redwood City 48
New York 47
Shenzhen 45
Duncan 40
Frankfurt 40
Santa Clara 40
Toronto 40
Buffalo 38
Guangzhou 36
Penza 36
San Francisco 35
Seoul 35
Fremont 32
Las Vegas 31
Neubiberg 31
Paris 31
London 30
Washington 28
Herkenbosch 27
Melun 26
Miami 26
Ottawa 26
Munich 25
St Petersburg 25
Falls Church 23
Moscow 23
Kraków 22
Norwalk 22
Stuttgart 22
Sofia 21
Tallinn 20
Varese 20
Porto Alegre 19
Andover 18
Chengdu 17
Collegno 17
Piscataway 17
San Jose 17
Hefei 16
Kiev 16
Modena 16
Studio City 16
Palermo 15
Podenzano 15
Frankfurt am Main 14
Fuzhou 14
Lappeenranta 14
Nanjing 14
San Antonio 14
Totale 23.308
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Nome #
Agri-Food Traceability Management using a RFID System with Privacy Protection 606
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 493
A SBST strategy to test microprocessors' branch target buffer 424
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors 423
Peak Power Estimation: A Case Study on CPU Cores 404
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers 404
On-line functionally untestable fault identification in embedded processor cores 401
An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs 380
On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors 379
An effective approach to automatic functional processor test generation for small-delay faults 373
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains 355
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-line Self-Test 354
Software-based self-test techniques of computational modules in dual issue embedded processors 353
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs 340
An Effective Methodology for On-line Testing of Embedded Microprocessors 336
On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors 333
A new hybrid fault detection technique for systems-on-a-chip 326
A Parallel Tester Architecture for Accelerometerand Gyroscope MEMS Calibration and Test 326
Software-based self-test of embedded microprocessors 325
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores 321
Integrating BIST techniques for on-line SoC testing 319
A Hybrid Approach for Detection and Correction of Transient Faults in SoCs 319
Design of an UHF RFID Transponder for Secure Authentication 318
An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices 317
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors 315
An efficient method for the test of embedded memory cores during the operational phase 310
Identification and classification of single-event upsets in the configuration memory of sram-based fpgas 309
An adaptive low-cost tester architecture supporting embedded memory volume diagnosis 307
A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC 306
An Optimized Test During Burn-In for Automotive SoC 305
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller 302
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques 296
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 292
SW-Based Transparent In-Field Memory Testing 290
Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems 289
Embedded Memory Diagnosis: An Industrial Workflow 284
An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores 279
System-in-package testing: problems and solutions 278
A Hybrid Approach to Fault Detection and Correction in SoCs 278
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core 276
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs 275
A new Architecture to Cross-Fertilize On-line and Manufacturing Testing 275
On the automation of the test flow of complex SoCs 273
A Programmable BIST for DRAM Testing and Diagnosis 272
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis 271
Diagnosing faulty functional units in processors by using automatically generated test sets 268
A System-layer Infrastructure for SoC Diagnosis 268
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores 267
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs 264
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test 262
A P1500-compatible programmable BIST approach for the test of embedded flash memories 262
Extended Fault Detection Techniques for Systems-on-Chip 261
A fault grading methodology for software-based self-test programs in systems-on-chip 260
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug 259
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In 258
On the evaluation of SEU sensitiveness in SRAM-based FPGAs 257
Using Infrastructure IPs to support SW-based Self-Test of Processor Cores 256
Microprocessor Testing: Functional Meets Structural Test 256
Test Techniques for System-on-Chip: Problems and solutions 255
An optimized hybrid approach to provide fault detection and correction in SoCs 254
Test, Reliability and Functional Safety trends for Automotive System-on-Chip 253
A pattern ordering algorithm for reducing the size of fault dictionaries 252
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications 252
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm 250
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers 249
Thermal issues in test: An overview of the significant aspects and industrial practice 249
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption 249
Testing logic cores using a BIST P1500 compliant approach: a case of study 249
In-field functional test programs development flow for embedded FPUs 247
Fault grading of software-based self-test procedures for dependable automotive applications 247
Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing 246
An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization 246
A tester architecture suitable for MEMS calibration and testing 245
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization 244
An effective ATPG flow for Gate Delay Faults 243
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC 242
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs 242
Exploiting an I-IP for both test and silicon debug of microprocessor cores 241
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA 241
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study 241
Optimized embedded memory diagnosis 240
Scan-Chain Intra-Cell Aware Testing 239
An integrated approach for increasing the soft-error detection capabilities in SoCs processors 239
Test Considerations about the Structured ASIC Paradigm 238
An Exact and Efficient Critical Path Tracing Algorithm 237
Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS) 237
An effective approach for functional test programs compaction 236
Evaluating Alpha-induced Soft Errors in Embedded Microprocessors 233
Exploiting an I-IP for In-field SOC test 232
Adaptive Management Techniques for Optimized Burn-In of Safety-Critical SoC 228
An adaptive tester architecture for volume diagnosis 227
An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs 226
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores 223
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults 220
SoC Symbolic Simulation: a case study on delay fault testing 219
A new DFM-proactive technique 218
An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives 218
A Tool for Supporting and Automating the Test of Complex System-on-Chips 215
Faster-than-at-speed execution of functional programs: an experimental analysis 215
Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs 214
Totale 28.400
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Categoria #
all - tutte 95.693
article - articoli 17.898
book - libri 735
conference - conferenze 74.549
curatela - curatele 0
other - altro 334
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.177
Totale 191.386
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20203.148 0 0 111 510 474 417 301 471 423 202 139 100
2020/20212.660 326 428 129 341 124 206 184 211 146 257 189 119
2021/20221.891 115 137 46 49 133 123 84 117 74 146 391 476
2022/20233.296 236 489 180 248 307 436 279 156 415 30 164 356
2023/20241.359 115 139 83 99 156 219 69 91 37 49 126 176
2024/20251.089 129 785 175 0 0 0 0 0 0 0 0 0
Totale 35.342