A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the causes for low functional testability and propose some techniques able to effectively face these issues. In particular, we describe a strategy to perform SBST on fully associative BTB units. The unit’s general structure is analyzed, a suitable test program is proposed and the strategy to observe the test responses is explained. Feasibility and effectiveness of the proposed approach are shown on a MIPS-like processor.

A SBST strategy to test microprocessors' branch target buffer / Bernardi, Paolo; Ciganda, LYL MERCEDES; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - STAMPA. - (2012), pp. 306-311. ((Intervento presentato al convegno IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012) tenutosi a Tallinn, Estonia nel April 18-20, 2012.

A SBST strategy to test microprocessors' branch target buffer

BERNARDI, PAOLO;CIGANDA, LYL MERCEDES;GROSSO, MICHELANGELO;SANCHEZ SANCHEZ, EDGAR ERNESTO;SONZA REORDA, Matteo
2012

Abstract

A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the causes for low functional testability and propose some techniques able to effectively face these issues. In particular, we describe a strategy to perform SBST on fully associative BTB units. The unit’s general structure is analyzed, a suitable test program is proposed and the strategy to observe the test responses is explained. Feasibility and effectiveness of the proposed approach are shown on a MIPS-like processor.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2495978
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