SANCHEZ SANCHEZ, EDGAR ERNESTO

SANCHEZ SANCHEZ, EDGAR ERNESTO  

Dipartimento di Automatica e Informatica  

Sanchez, Ernesto; E. Sanchez; Sanchez E.; Ernesto Sanchez; SANCHEZ EDGAR; SANCHEZ E.; SANCHEZ SANCHEZ EDGAR ERNESTO; SANCHEZ SANCHEZ E.  

012684  

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Citazione Data di pubblicazione Autori File
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores / Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2009), pp. 103-108. ((Intervento presentato al convegno 9th International Workshop on Microprocessor Test and Verification (MTV'08) tenutosi a Austin, TX (U.S.A.) nel 8-10 Dic., 2008 [10.1109/MTV.2008.9]. 1-gen-2009 BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo -
A fault grading methodology for software-based self-test programs in systems-on-chip / Ballan, O.; Bernardi, Paolo; Fontana, G.; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO. - (2010), pp. 43-46. ((Intervento presentato al convegno International Workshop on Microprocessor Test and Verification tenutosi a Austin (TX), USA nel Dec. 13-15, 2010 [10.1109/MTV.2010.16]. 1-gen-2010 BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTO + -
A Framework for Automated Detection of Power-Related Software Errors in Industrial Verification Processes / Gandini, S.; Ruzzarin, W.; SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; Tonda, ALBERTO PAOLO. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - STAMPA. - 26:(2010), pp. 689-697. [10.1007/s10836-010-5184-5] 1-gen-2010 SANCHEZ SANCHEZ, EDGAR ERNESTOSQUILLERO, GiovanniTONDA, ALBERTO PAOLO + jetta2010.pdf
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing / M., Valka; A., Bosio; L., Dilillo; P., Girard; S., Pravossoudovitch; A., Virazel; SANCHEZ SANCHEZ, EDGAR ERNESTO; DE CARVALHO, Mauricio; SONZA REORDA, Matteo. - (2011), pp. 153-158. ((Intervento presentato al convegno 2011 16th IEEE European Test Symposium (ETS) [10.1109/ETS.2011.21]. 1-gen-2011 SANCHEZ SANCHEZ, EDGAR ERNESTODE CARVALHO, MAURICIOSONZA REORDA, Matteo + -
A hardware accelerated framework for the generation of design validation programs for SMT processors / SANCHEZ SANCHEZ, EDGAR ERNESTO; Danilo, Ravotto; SONZA REORDA, Matteo. - (2010). ((Intervento presentato al convegno 13th IEEE International Symposium on Design & Diagnostics of Elctronic Circuits and Systems tenutosi a Vienna, Austria nel April 2010. 1-gen-2010 SANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs / PEREZ W., J; VELASCO MEDINA, J; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2008), pp. 143-148. ((Intervento presentato al convegno IOLTS 2008: IEEE International On-line Testing Symposium. 1-gen-2008 RAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -
A local analysis of an incremental evolutionary tool for processor diagnosis / Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni. - (2007), pp. 3467-3473. ((Intervento presentato al convegno IEEE Congress on Evolutionary Computation, 2007. CEC 2007 tenutosi a Singapore nel 25-28 Sept. 2007 [10.1109/CEC.2007.4424921]. 1-gen-2007 RAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSQUILLERO, Giovanni 1648932.pdf
A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems / SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; Violante, Massimo. - (2004), pp. 871-878. ((Intervento presentato al convegno Congress on Evolutionary Computation [10.1109/CEC.2004.1330952]. 1-gen-2004 SANCHEZ SANCHEZ, EDGAR ERNESTOSQUILLERO, GiovanniVIOLANTE, MASSIMO -
A modular Architecture for a Populationless Evolutionary Algorithm for MIP / SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni. - (2005). ((Intervento presentato al convegno GSICE05: Giornata di Studio Italiana sul Calcolo Evolutivo tenutosi a Milano nel September 20 2005. 1-gen-2005 SANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSQUILLERO, Giovanni -
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm / Christou, K; MICHAEL M., K; Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2008), pp. 389-394. ((Intervento presentato al convegno 26th IEEE VLSI Test Symposium tenutosi a San Diego, CA, USA nel apr 27 - may 1 [10.1109/VTS.2008.37]. 1-gen-2008 BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -
A SBST strategy to test microprocessors' branch target buffer / Bernardi, Paolo; Ciganda, LYL MERCEDES; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - STAMPA. - (2012), pp. 306-311. ((Intervento presentato al convegno IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012) tenutosi a Tallinn, Estonia nel April 18-20, 2012. 1-gen-2012 BERNARDI, PAOLOCIGANDA, LYL MERCEDESGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo -
A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions / VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2007), pp. 348-353. ((Intervento presentato al convegno SBCCI2007: ACM 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN. 1-gen-2007 VEIRAS BOLZANI, Leticia MariaSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo -
A Software-based self-test methodology for system peripherals / Grosso, Michelangelo; W. J. Perez, H.; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; J., Velasco Medina. - STAMPA. - (2010), pp. 195-200. ((Intervento presentato al convegno 15th IEEE European Test Symposium (ETS) tenutosi a Prague (Czech Republic) nel May 2010. 1-gen-2010 GROSSO, MICHELANGELORAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -
A survey of µGP / SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano. - vol.1, issue 2:(2006), pp. 17-21. 1-gen-2006 SANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANO -
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications / Cantoro, R.; Firrincieli, Andrea; Piumatti, D.; Restifo, M.; Sanchez, E.; Reorda, M. Sonza. - STAMPA. - 2018-:(2018), pp. 1-6. ((Intervento presentato al convegno 19th IEEE Latin-American Test Symposium, LATS 2018 tenutosi a bra nel 2018 [10.1109/LATW.2018.8349679]. 1-gen-2018 Cantoro, R.FIRRINCIELI, ANDREAPiumatti, D.Restifo, M.Sanchez, E.Reorda, M. Sonza 08349679.pdflats18 preprint.pdf
About Performance Faults in Microprocessor Core in-field Testing / Acle, Julio Perez; Sanchez, Ernesto; Reorda, Matteo Sonza. - STAMPA. - (2019), pp. 229-232. ((Intervento presentato al convegno 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) [10.1109/LASCAS.2019.8667562]. 1-gen-2019 Acle, Julio PerezSanchez, ErnestoReorda, Matteo Sonza lascas 2019 preprint 2.pdf
About the functional test of permanent faults in distributed systems / Vaskova, A.; Portela García, M.; López Ongil, C.; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - STAMPA. - (2015). ((Intervento presentato al convegno 2015 Conference on Design of Circuits and Integrated Systems (DCIS) [10.1109/DCIS.2015.7388571]. 1-gen-2015 SANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + 07388571.pdf
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores / VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, Matteo; Squillero, Giovanni. - (2007), pp. 265-270. ((Intervento presentato al convegno IOLTS2007: IEEE International On-Line Testing Symposium tenutosi a Hersonissos-Heraklion, Crete, Greece nel 8-11 July 2007 [10.1109/IOLTS.2007.14]. 1-gen-2007 VEIRAS BOLZANI, Leticia MariaSANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSONZA REORDA, MatteoSQUILLERO, Giovanni -
An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization / Appello, D; Bernardi, Paolo; Bruno, M; Cagliesi, R; Giancarlini, M; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2008). ((Intervento presentato al convegno 2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020. 1-gen-2008 BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains / LAGOS BENITES, J; Appello, D; Bernardi, Paolo; Grosso, Michelangelo; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2007), pp. 291-299. ((Intervento presentato al convegno DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 1-gen-2007 BERNARDI, PAOLOGROSSO, MICHELANGELORAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + -