An Integrated Environment for the Reliability Assessment of CNNs Accelerators Implemented in FPGAs

This work presents the development of an integrated framework that facilitates the resilience evaluation of CNNs w.r.t. hardware faults by resorting to fault emulation strategies. The proposed framework leverages the flexibility of Field-Programmable Gate-Arrays (FPGAs) to implement and evaluate any DL accelerator architecture. In addition, we describe the detailed procedure to emulate faults inside a DL architecture. We report the cost, simulation time, and hardware overhead required by the proposed technique when using a stream-processing DL accelerator to deploy some of the most relevant layers of LeNet5. The experimental results were gathered in four different FPGA-based platforms, demonstrating the flexibility of the proposed approach.