Archivio Istituzionale della RicercaFARNAGHINEJAD, BEHNAM
FARNAGHINEJAD, BEHNAM
Dipartimento di Automatica e Informatica
097287
Case Study: Integrating RISC-V Zicfiss Shadow Stack Support for Control-Flow Integrity on the CVA6 Processor
2026 Farnaghinejad, Behnam; Sanchez, Ernesto
Deep Learning-Based Power Side-Channel Evaluation from RTL Switching-Activity Proxies
2026 Farnaghinejad, Behnam; Ruospo, Annachiara; Savino, Alessandro; Di Carlo, Stefano; Sanchez, Ernesto
Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level
2025 Farnaghinejad, Behnam; Porsia, Antonio; Ruospo, Annachiara; Savino, Alessandro; Di Carlo, Stefano; Sanchez, Ernesto
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
2025 Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, Antonio; Ruospo, Annachiara; Di Carlo, Stefano; Savino, Alessandro; Sanchez, Ernesto
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Case Study: Integrating RISC-V Zicfiss Shadow Stack Support for Control-Flow Integrity on the CVA6 Processor / Farnaghinejad, Behnam; Sanchez, Ernesto. - ELETTRONICO. - (2026), pp. 1-2. ( 27th IEEE Latin American Test Symposium (LATS 2026) Florianópolis (BRA) 17-20 March 2026) [10.1109/lats70329.2026.11480312]. | 1-gen-2026 | Farnaghinejad, BehnamSanchez, Ernesto | Case_Study_Integrating_RISC-V_Zicfiss_Shadow_Stack_Support_for_Control-Flow_Integrity_on_the_CVA6_Processor.pdf; Case_Study__LATS2026__Integrating_RISC_V_Zicfiss_Shadow_Stack_Support_for_Control_Flow_Integrity_on_the_CVA6_Processor.pdf |
| Deep Learning-Based Power Side-Channel Evaluation from RTL Switching-Activity Proxies / Farnaghinejad, Behnam; Ruospo, Annachiara; Savino, Alessandro; Di Carlo, Stefano; Sanchez, Ernesto. - ELETTRONICO. - (2026), pp. 1-6. ( 27th IEEE Latin American Test Symposium (LATS 2026) Florianópolis (BRA) 17-20 March 2026) [10.1109/lats70329.2026.11480302]. | 1-gen-2026 | Farnaghinejad, BehnamRuospo, AnnachiaraSavino, AlessandroDi Carlo, StefanoSanchez, Ernesto | Paper__LATS2026__Deep_Learning_Based_Power_Side_Channel_Evaluation_from_RTL_Switching_Activity_Proxies.pdf; Deep_Learning-Based_Power_Side-Channel_Evaluation_from_RTL_Switching-Activity_Proxies.pdf |
| Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level / Farnaghinejad, Behnam; Porsia, Antonio; Ruospo, Annachiara; Savino, Alessandro; Di Carlo, Stefano; Sanchez, Ernesto. - ELETTRONICO. - (2025), pp. 1-2. ( 26th IEEE Latin American Test Samposium 2025 San Andres Islas (COL) 11-14 March 2025) [10.1109/lats65346.2025.10963943]. | 1-gen-2025 | Farnaghinejad, BehnamPorsia, AntonioRuospo, AnnachiaraSavino, AlessandroDi Carlo, StefanoSanchez, Ernesto | LATS2025_IRIS.pdf; Late_Contribution_VeriSide_A_Modified_Verilator_for_Leakage_Assessment_at_the_RTL_Level.pdf |
| Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) / Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, Antonio; Ruospo, Annachiara; Di Carlo, Stefano; Savino, Alessandro; Sanchez, Ernesto. - (2025), pp. 233-242. ( International Test Conference 2025 San Diego, California (USA) September 20-26, 2025) [10.1109/ITC58126.2025.00030]. | 1-gen-2025 | Behnam FarnaghinejadAlessandra DolmetaGuido MaseraAntonio PorsiaAnnachiara RuospoStefano Di CarloAlessandro SavinoErnesto Sanchez + | ITC2025___Power_Side_Channel_Vulnerabilities_of_a_RISC_V_Cryptography_Accelerator_Integrated_into_CVA6_via_CV_X_IF.pdf; Power_Side-Channel_Vulnerabilities_of_a_RISC-V_Cryptography_Accelerator_Integrated_into_CVA6_via_Core-V_eXtension_Interface_CV-X-IF.pdf |