Archivio Istituzionale della RicercaMASERA, Guido
MASERA, Guido
Dipartimento di Elettronica e Telecomunicazioni
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Risultati 1 - 20 di 314 (tempo di esecuzione: 0.039 secondi).
A Lightweight Accelerator for the LESS Digital Signature Scheme
2026 Cutrera, Giuseppe; Dolmeta, Alessandra; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
ANT-V: A Monolithic RISC-V Vector Processor for Machine Learning at the Edge
2026 Guella, Flavia; Caviglia, Alessio; Caon, Michele; Carlo, Stefano Di; Masera, Guido; Martina, Maurizio
CIRCE CROSS Integrated RISC-V Cryptographic Extension
2026 Dolmeta, Alessandra; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon
2026 Mirigaldi, Mattia; Paninforni, Nico; Martina, Maurizio; Masera, Guido
PolHEEPo: A 65 nm 6mm2 RISC-V SoC Filling the Gap Between Cloud and Edge Computing
2026 Giuffrida, Luigi; Dolmeta, Alessandra; Naclerio, Alessio; Piscopo, Valeria; Mirigaldi, Mattia; Manfredi, Enrico; Varaldi, Alessandro; Petrolo, Vincenzo; Guella, Flavia; Vacca, Marco; Masera, Guido; Martina, Maurizio
A Deep Dive into Integration Methodologies in RISC-V
2025 Piscopo, Valeria; Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA
2025 Piscopo, Valeria; Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
2025 Petrolo, Vincenzo; Guella, Flavia; Caon, Michele; Schiavone, Pasquale Davide; Masera, Guido; Martina, Maurizio
CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
2025 Dolmeta, Alessandra; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography
2025 Dolmeta, Alessandra; Martina, Maurizio; Masera, Guido
Just TestIt! An SBST Approach To Automate System-Integration Testing
2025 Terzano, Tommaso; Giuffrida, Luigi; Sapriza, Juan; Schiavone, Pasquale Davide; Masera, Guido; Atienza, David; Lavagno, Luciano; Martina, Maurizio
Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack
2025 Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
2025 Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, Antonio; Ruospo, Annachiara; Di Carlo, Stefano; Savino, Alessandro; Sanchez, Ernesto
RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards
2025 Dolmeta, Alessandra; Piscopo, Valeria; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
Scalability analysis of multi-bank near-memory computing in low-power SoCs
2025 Giuffrida, Luigi; Schiavone, Pasquale Davide; Caon, Michele; Masera, Guido; Martina, Maurizio; Atienza, David
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
2025 Caon, M.; Chone, C.; Schiavone, P. D.; Levisse, A.; Masera, G.; Martina, M.; Atienza, D.
Stop Wasting your Cache! Bringing Machine Learning into Cache Computing
2025 Petrolo, Vincenzo; Guella, Flavia; Caon, Michele; Masera, Guido; Martina, Maurizio
The Quest for Efficient ASCON Implementations: A Comprehensive Review of Implementation Strategies and Challenges
2025 Mirigaldi, Mattia; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems
2025 Ressa, Eugenio; Marchisio, Alberto; Martina, Maurizio; Masera, Guido; Shafique, Muhammad
TOXOS: Spinning Up Nonlinearity in On-Vehicle Inference with a RISC-V CORDIC Coprocessor
2025 Giuffrida, Luigi; Masera, Guido; Martina, Maurizio
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Lightweight Accelerator for the LESS Digital Signature Scheme / Cutrera, G., Dolmeta, A., Piscopo, V., Martina, M., Masera, G.. - In: CRYPTOGRAPHY. - ISSN 2410-387X. - 10:4(2026). [10.3390/cryptography10040045] | 1-gen-2026 | Cutrera, GiuseppeDolmeta, AlessandraPiscopo, ValeriaMartina, MaurizioMasera, Guido | cryptography-10-00045.pdf |
| ANT-V: A Monolithic RISC-V Vector Processor for Machine Learning at the Edge / Guella, F., Caviglia, A., Caon, M., Carlo, S.D., Masera, G., Martina, M.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - (2026), pp. 1-1. [10.1109/tcsii.2026.3733550] | 1-gen-2026 | Guella, FlaviaCaviglia, AlessioCaon, MicheleCarlo, Stefano DiMasera, GuidoMartina, Maurizio | ANT-V_A_Monolithic_RISC-V_Vector_Processor_for_Machine_Learning_at_the_Edge.pdf; ANT_V_final (1) (1).pdf |
| CIRCE CROSS Integrated RISC-V Cryptographic Extension / Dolmeta, A., Piscopo, V., Martina, M., Masera, G.. - ELETTRONICO. - (2026), pp. 1-3. (2026 Design, Automation & Test in Europe Conference (DATE) Verona (Ita) 20 - 23 April 2026) [10.23919/date69613.2026.11539337]. | 1-gen-2026 | Dolmeta, AlessandraPiscopo, ValeriaMartina, MaurizioMasera, Guido | CIRCE_CROSS_Integrated_RISC-V_Cryptographic_Extension.pdf; DATE_extended_abstract.pdf |
| Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon / Mirigaldi, M., Paninforni, N., Martina, M., Masera, G.. - ELETTRONICO. - (2026). (2026 Design, Automation & Test in Europe Conference (DATE) Verona (Ita) 20 - 22 Aprile 2026) [10.23919/date69613.2026.11539534]. | 1-gen-2026 | Mirigaldi, MattiaPaninforni, NicoMartina, MaurizioMasera, Guido | 878.pdf; DATE_ASCON_paper-1.pdf |
| PolHEEPo: A 65 nm 6mm2 RISC-V SoC Filling the Gap Between Cloud and Edge Computing / Giuffrida, L., Dolmeta, A., Naclerio, A., Piscopo, V., Mirigaldi, M., Manfredi, E., Varaldi, A., Petrolo, V., Guella, F., Vacca, M., Masera, G., Martina, M.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - (2026), pp. 1-1. [10.1109/TCSII.2026.3735193] | 1-gen-2026 | Luigi GiuffridaAlessandra DolmetaAlessio NaclerioValeria PiscopoMattia MirigaldiEnrico ManfrediAlessandro VaraldiVincenzo PetroloFlavia GuellaMarco VaccaGuido MaseraMaurizio Martina | - |
| A Deep Dive into Integration Methodologies in RISC-V / Piscopo, V., Dolmeta, A., Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 30-33. (22nd ACM International Conference on Computing Frontiers Cagliari (Ita) May 28-30, 2025) [10.1145/3706594.3726969]. | 1-gen-2025 | Piscopo, ValeriaDolmeta, AlessandraMirigaldi, MattiaMartina, MaurizioMasera, Guido | 3706594-3726969.pdf |
| A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA / Piscopo, V., Dolmeta, A., Mirigaldi, M., Martina, M., Masera, G.. - In: SENSORS. - ISSN 1424-8220. - ELETTRONICO. - 25:6(2025). [10.3390/s25061678] | 1-gen-2025 | Piscopo, ValeriaDolmeta, AlessandraMirigaldi, MattiaMartina, MaurizioMasera, Guido | sensors-25-01678-v2.pdf |
| ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions / Petrolo, V., Guella, F., Caon, M., Schiavone, P.D., Masera, G., Martina, M.. - (2025), pp. 1-6. (62nd ACM/IEEE Design Automation Conference (DAC 2025) San Francisco (USA) 22-25 June 2025) [10.1109/dac63849.2025.11132598]. | 1-gen-2025 | Petrolo, VincenzoGuella, FlaviaCaon, MicheleMasera, GuidoMartina, Maurizio + | ARCANE_Adaptive_RISC-V_Cache_Architecture_for_Near-memory_Extensions (1).pdf |
| CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON / Dolmeta, A., Piscopo, V., Martina, M., Masera, G.. - ELETTRONICO. - 1:(2025), pp. 1-6. (IEEE Computer Society Annual Symposium on VLSI Kalamata (Gre) July 6-9, 2025) [10.1109/ISVLSI65124.2025.11130264]. | 1-gen-2025 | Dolmeta,AlessandraPiscopo,ValeriaMartina,MaurizioMasera,Guido | 25_ISVLSI.pdf; CHIMERA_Cryptographic_Hardware_for_Integrated_Multipurpose_Engine_on_RISC-V_with_ASCON.pdf |
| Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography / Dolmeta, A., Martina, M., Masera, G.. - ELETTRONICO. - 1369:(2025), pp. 39-47. (Applications in Electronics Pervading Industry, Environment and Society, ApplePies 2024 Torino (Ita) 19-20 September 2024) [10.1007/978-3-031-84100-2_5]. | 1-gen-2025 | Dolmeta, AlessandraMartina, MaurizioMasera, Guido | 24_ApplePies.pdf; versione_editoriale.pdf |
| Just TestIt! An SBST Approach To Automate System-Integration Testing / Terzano, T., Giuffrida, L., Sapriza, J., Schiavone, P.D., Masera, G., Atienza, D., Lavagno, L., Martina, M.. - (2025), pp. 74-77. (22nd ACM International Conference on Computing Frontiers Cagliari (Ita) May 28–30, 2025) [10.1145/3706594.3726980]. | 1-gen-2025 | Terzano, TommasoGiuffrida, LuigiMasera, GuidoAtienza, DavidLavagno, LucianoMartina, Maurizio + | ACM_OSHW25___TestIt.pdf; 3706594.3726980.pdf |
| Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack / Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 19-27. (Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES Torino (Ita) 19-20 September 2024) [10.1007/978-3-031-84100-2_3]. | 1-gen-2025 | Mirigaldi, MattiaMartina, MaurizioMasera, Guido | Performance_Comparison__Software_vs__Hardware_Implementation_of_Novel_S_Box_Designed_to_Resist_Power_Analysis_Attack.pdf; versione_editoriale_compressed.pdf |
| Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) / Farnaghinejad, B., Bellizia, D., Dolmeta, A., Masera, G., Porsia, A., Ruospo, A., Di Carlo, S., Savino, A., Sanchez, E.. - (2025), pp. 233-242. (International Test Conference 2025 San Diego, California (USA) September 20-26, 2025) [10.1109/ITC58126.2025.00030]. | 1-gen-2025 | Behnam FarnaghinejadAlessandra DolmetaGuido MaseraAntonio PorsiaAnnachiara RuospoStefano Di CarloAlessandro SavinoErnesto Sanchez + | ITC2025___Power_Side_Channel_Vulnerabilities_of_a_RISC_V_Cryptography_Accelerator_Integrated_into_CVA6_via_CV_X_IF.pdf; Power_Side-Channel_Vulnerabilities_of_a_RISC-V_Cryptography_Accelerator_Integrated_into_CVA6_via_Core-V_eXtension_Interface_CV-X-IF.pdf |
| RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards / Dolmeta, A., Piscopo, V., Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 1-5. (2025 IEEE International Symposium on Circuits and Systems Londra (UK) May 25-28, 2025) [10.1109/iscas56072.2025.11043433]. | 1-gen-2025 | Dolmeta, AlessandraPiscopo, ValeriaMirigaldi, MattiaMartina, MaurizioMasera, Guido | RISC-V_Based_Keccak_Co-Processor_for_NIST_Post-Quantum_Cryptography_Standards.pdf; ISCAS2025 (1).pdf |
| Scalability analysis of multi-bank near-memory computing in low-power SoCs / Giuffrida, L., Schiavone, P.D., Caon, M., Masera, G., Martina, M., Atienza, D.. - (2025), pp. 1-4. (33rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2025 chl 2025) [10.1109/vlsi-soc64688.2025.11421768]. | 1-gen-2025 | Giuffrida, LuigiCaon, MicheleMasera, GuidoMartina, MaurizioAtienza, David + | - |
| Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes / Caon, M., Chone, C., Schiavone, P.D., Levisse, A., Masera, G., Martina, M., Atienza, D.. - In: IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING. - ISSN 2168-6750. - ELETTRONICO. - 13:3(2025), pp. 1003-1018. [10.1109/TETC.2025.3555869] | 1-gen-2025 | Masera G.Martina M. + | TETC25.pdf; NearMemory_authors.pdf |
| Stop Wasting your Cache! Bringing Machine Learning into Cache Computing / Petrolo, V., Guella, F., Caon, M., Masera, G., Martina, M.. - 2:(2025), pp. 86-89. (22nd ACM International Conference on Computing Frontiers 2025, CF 2025 Cagliari (Ita) 28-30 Maggio 2025) [10.1145/3706594.3726983]. | 1-gen-2025 | Petrolo, VincenzoGuella, FlaviaCaon, MicheleMasera, GuidoMartina, Maurizio | 3706594.3726983 (1).pdf |
| The Quest for Efficient ASCON Implementations: A Comprehensive Review of Implementation Strategies and Challenges / Mirigaldi, M., Piscopo, V., Martina, M., Masera, G.. - In: CHIPS. - ISSN 2674-0729. - ELETTRONICO. - 4:2(2025), pp. 1-29. [10.3390/chips4020015] | 1-gen-2025 | Mirigaldi, MattiaPiscopo, ValeriaMartina, MaurizioMasera, Guido | CHIPS___Ascon_survey.pdf; chips-04-00015-v2.pdf |
| TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems / Ressa, E., Marchisio, A., Martina, M., Masera, G., Shafique, M.. - ELETTRONICO. - (2025), pp. 1-7. (2025 International Joint Conference on Neural Networks (IJCNN) Rome (Ita) 30 giugno - 5 luglio 2025) [10.1109/ijcnn64981.2025.11228478]. | 1-gen-2025 | Martina, MaurizioMasera, Guido + | TinyCL.pdf; IJCNN_25_TinyCL_pdfexpress.pdf |
| TOXOS: Spinning Up Nonlinearity in On-Vehicle Inference with a RISC-V CORDIC Coprocessor / Giuffrida, L., Masera, G., Martina, M.. - In: TECHNOLOGIES. - ISSN 2227-7080. - 13:10(2025). [10.3390/technologies13100479] | 1-gen-2025 | Luigi, GiuffridaGuido, MaseraMaurizio, Martina | technologies-13-00479.pdf |