This work presents a unified RISC-V extension for Post-Quantum Cryptography (PQC) that emphasizes versatility and openness. The design exposes a compact set of custom scalar instructions via the Core-V eXtension Interface (CV-X-IF) and a modular PQ-ALU that accelerates the dominant kernels across hash-, lattice-, and code-based schemes: Keccak processing, randomness sampling, modular and polynomial arithmetic, finite-field operations, and coefficient compression. The system supports algorithms standardized by NIST, ML-KEM, ML-DSA, SLH-DSA, and HQC, as well as candidates under evaluation. The full hardware and software stack is released as open source to enable reproducibility and community reuse. We provide ASIC results from post-synthesis characterization in 65 nm CMOS, reporting instruction-cycle counts, along with power and energy estimates for each custom operation. Overall, the proposed extension delivers a compact (26.3 kGE) and practical path to crypto-agile, energy-efficient PQC on RISC-V while preserving software compatibility and a clean integration into existing cores.

Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography / Dolmeta, A., Piscopo, V., Martina, M., Masera, G., Hutter, M.. - ELETTRONICO. - (2026). (Design and Automation Conference 2026 Long Beach, CA, USA ) [10.1145/3770743.3804373].

Raise the Shields: A Modular RISC-V Extension for Post Quantum Cryptography

Dolmeta,Alessandra;Piscopo,Valeria;Martina,Maurizio;Masera,Guido;
2026

Abstract

This work presents a unified RISC-V extension for Post-Quantum Cryptography (PQC) that emphasizes versatility and openness. The design exposes a compact set of custom scalar instructions via the Core-V eXtension Interface (CV-X-IF) and a modular PQ-ALU that accelerates the dominant kernels across hash-, lattice-, and code-based schemes: Keccak processing, randomness sampling, modular and polynomial arithmetic, finite-field operations, and coefficient compression. The system supports algorithms standardized by NIST, ML-KEM, ML-DSA, SLH-DSA, and HQC, as well as candidates under evaluation. The full hardware and software stack is released as open source to enable reproducibility and community reuse. We provide ASIC results from post-synthesis characterization in 65 nm CMOS, reporting instruction-cycle counts, along with power and energy estimates for each custom operation. Overall, the proposed extension delivers a compact (26.3 kGE) and practical path to crypto-agile, energy-efficient PQC on RISC-V while preserving software compatibility and a clean integration into existing cores.
2026
9798400722547
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/3016929
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