PolHEEPo: A 65 nm 6mm2 RISC-V SoC Filling the Gap Between Cloud and Edge Computing

This paper presents PolHEEPo, a heterogeneous RISC-V System-on-Chip (SoC) jointly supporting machine-learning (ML) inference and on-node protection of telemetry payloads in battery-powered edge devices. Fabricated in 65 nm TSMC LP technology, the 6 mm2 die extends X-HEEP with memory-mapped accelerators for ML, authenticated encryption, SHA-3 hashing, and PUF-based hardware identity. These include Rogue, a streaming 4 × 4 Coarse-Grain Reconfigurable Array (CGRA) for GEMM and nonlinear activations; Ascon and Keccak engines; and PUFfo, a ring-oscillator Physical Unclonable Function providing a hardware identity primitive. Operating from 0.8 V to 1.2 V at up to 120 MHz, PolHEEPo is evaluated on industrial predictive-maintenance and wearable cardiac-monitoring workloads combining on-device inference with a hardware-accelerated hashing and authenticated encryption pipeline. Silicon measurements show that execution using accelerators lowers the energy of the offloaded stages by 69% and 86%, while complete-window energy decreases from 2.81 mJ to 2.53 mJ and from 5.51 mJ to 2.80 mJ, respectively. For the cardiac monitor, accelerator offloading approximately halves both application-level energy and latency, yielding a projected battery autonomy of 6.5 days. To our knowledge, among the published silicon platforms considered, PolHEEPo is distinguished by jointly integrating on-device ML acceleration, lightweight authenticated encryption, a PQC-relevant Keccak/SHA-3 primitive, and a hardware identity primitive within a RISC-V SoC.