ANT-V: A Monolithic RISC-V Vector Processor for Machine Learning at the Edge

The shift towards edge computing, coupled with the increasing adoption of Machine Learning (ML) for data-intensive tasks, imposes demanding performance requirements on embedded systems, where employing dedicated accelerators is often impractical due to tight power and area budgets. To address these challenges, we present ANT-V, a lightweight RISC-V vector processor designed to efficiently execute data-parallel workloads within the tight resource budgets of edge platforms. ANT-V integrates a selected subset of the Zve32x vector extension into the open-source CVE2 core, adopting a monolithic, zero-duplication approach. To minimize hardware overhead, vector instructions execute as controller-driven micro-sequences over the scalar datapath, avoiding duplication of functional units. To eliminate the cost of a dedicated Vector Register File, vector registers are mapped to a software-reconfigurable region of the on-chip SRAM, trading raw bandwidth for area efficiency and runtime flexibility. Post-layout evaluation in 65nm CMOS shows negligible system-level area overhead, with up to 17x higher throughput and 16x better energy efficiency compared to the scalar baseline on ML kernels. These results position ANT-V as an effective compromise, enabling faster edge ML inference on general-purpose embedded systems without the additional complexity of specialized hardware.