Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography

The development of embedded systems has notably evolved, emphasizing the inclusion of specialized accelerators within microcon-trollers to enhance performance and efficiency. A key factor in this inte-gration is the level of connectivity between the central processing unit (CPU) and these accelerators, as well as the specific type of data being handled. This article presents a method to tailor a RISC-V instruction set to specific requirements, enhancing performance while preserving flex-ibility; this method is explored on a relevant case of study, the Keccak cryptographic hash function. By leveraging the CV32E40PX core and the Core-V eXtension Interface (CV-X-IF), this approach introduces innovative opportunities in accelerator integration. The CV-X-IF sim-plifies the addition of new instructions to the Instruction Set Architec-ture (ISA) and streamlines the integration of tightly coupled accelera-tors.Consequently,theseacceleratorsbecomemoreadaptableandcanbeemployedwithanyRISC-Vcore,broadeningtheirapplicabilityandpotentialimpact.Experimentalresultsareanalyzedandcomparedwithrespecttothesameaccelerator,integratedasloosely-coupledacceler-atorusingtheExtendibleAcceleratorInterface(XAIF).Moreover,thedesignedRISC-Vunitsarelikenedtootherimplementationsavailableintheliteraturetohighlightthepotentialoftheadoptedmethod