Archivio Istituzionale della RicercaMASERA, Guido
MASERA, Guido
Dipartimento di Elettronica e Telecomunicazioni
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Risultati 1 - 20 di 308 (tempo di esecuzione: 0.027 secondi).
CIRCE CROSS Integrated RISC-V Cryptographic Extension
2026 Dolmeta, Alessandra; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon
2026 Mirigaldi, Mattia; Paninforni, Nico; Martina, Maurizio; Masera, Guido
A Deep Dive into Integration Methodologies in RISC-V
2025 Piscopo, Valeria; Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA
2025 Piscopo, Valeria; Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
2025 Dolmeta, Alessandra; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography
2025 Dolmeta, Alessandra; Martina, Maurizio; Masera, Guido
Just TestIt! An SBST Approach To Automate System-Integration Testing
2025 Terzano, Tommaso; Giuffrida, Luigi; Sapriza, Juan; Schiavone, Pasquale Davide; Masera, Guido; Atienza, David; Lavagno, Luciano; Martina, Maurizio
Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack
2025 Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
2025 Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, Antonio; Ruospo, Annachiara; Di Carlo, Stefano; Savino, Alessandro; Sanchez, Ernesto
RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards
2025 Dolmeta, Alessandra; Piscopo, Valeria; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
2025 Caon, M.; Chone, C.; Schiavone, P. D.; Levisse, A.; Masera, G.; Martina, M.; Atienza, D.
The Quest for Efficient ASCON Implementations: A Comprehensive Review of Implementation Strategies and Challenges
2025 Mirigaldi, Mattia; Piscopo, Valeria; Martina, Maurizio; Masera, Guido
TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems
2025 Ressa, Eugenio; Marchisio, Alberto; Martina, Maurizio; Masera, Guido; Shafique, Muhammad
TOXOS: Spinning Up Nonlinearity in On-Vehicle Inference with a RISC-V CORDIC Coprocessor
2025 Giuffrida, Luigi; Masera, Guido; Martina, Maurizio
TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography
2025 Dolmeta, Alessandra; Di Matteo, Stefano; Valea, Emanuele; Carmona, Mikael; Loiseau, Antoine; Martina, Maurizio; Masera, Guido
ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms exploiting new CV-X-IF Interface
2024 Dolmeta, Alessandra; Martina, Maurizio; Masera, Guido
Ditching the Queue: Optimizing Coprocessor Utilization with Out-of-Order CPUs on compact Systems on Chip
2024 Caon, Michele; Masera, Guido; Martina, Maurizio
Hardware and Software Optimizations for Capsule Networks
2024 Marchisio, Alberto; Bussolino, Beatrice; Colucci, Alessio; Mrazek, Vojtech; Hanif, Muhammad Abdullah; Martina, Maurizio; Masera, Guido; Shafique, Muhammad
Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber
2024 Dolmeta, Alessandra; Valpreda, Emanuele; Martina, Maurizio; Masera, Guido
LOKI Low-Latency Open-Source Kyber-Accelerator IPs
2024 Dolmeta, Alessandra; Mirigaldi, Mattia; Martina, Maurizio; Masera, Guido
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| CIRCE CROSS Integrated RISC-V Cryptographic Extension / Dolmeta, A., Piscopo, V., Martina, M., Masera, G.. - ELETTRONICO. - (2026), pp. 1-3. (2026 Design, Automation & Test in Europe Conference (DATE) Verona (Ita) 20 - 23 April 2026) [10.23919/date69613.2026.11539337]. | 1-gen-2026 | Dolmeta, AlessandraPiscopo, ValeriaMartina, MaurizioMasera, Guido | CIRCE_CROSS_Integrated_RISC-V_Cryptographic_Extension.pdf; DATE_extended_abstract.pdf |
| Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon / Mirigaldi, M., Paninforni, N., Martina, M., Masera, G.. - ELETTRONICO. - (2026). (2026 Design, Automation & Test in Europe Conference (DATE) Verona (Ita) 20 - 22 Aprile 2026) [10.23919/date69613.2026.11539534]. | 1-gen-2026 | Mirigaldi, MattiaPaninforni, NicoMartina, MaurizioMasera, Guido | 878.pdf; DATE_ASCON_paper-1.pdf |
| A Deep Dive into Integration Methodologies in RISC-V / Piscopo, V., Dolmeta, A., Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 30-33. (22nd ACM International Conference on Computing Frontiers Cagliari (Ita) May 28-30, 2025) [10.1145/3706594.3726969]. | 1-gen-2025 | Piscopo, ValeriaDolmeta, AlessandraMirigaldi, MattiaMartina, MaurizioMasera, Guido | 3706594-3726969.pdf |
| A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA / Piscopo, V., Dolmeta, A., Mirigaldi, M., Martina, M., Masera, G.. - In: SENSORS. - ISSN 1424-8220. - ELETTRONICO. - 25:6(2025). [10.3390/s25061678] | 1-gen-2025 | Piscopo, ValeriaDolmeta, AlessandraMirigaldi, MattiaMartina, MaurizioMasera, Guido | sensors-25-01678-v2.pdf |
| CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON / Dolmeta, A., Piscopo, V., Martina, M., Masera, G.. - ELETTRONICO. - 1:(2025), pp. 1-6. (IEEE Computer Society Annual Symposium on VLSI Kalamata (Gre) July 6-9, 2025) [10.1109/ISVLSI65124.2025.11130264]. | 1-gen-2025 | Dolmeta,AlessandraPiscopo,ValeriaMartina,MaurizioMasera,Guido | 25_ISVLSI.pdf; CHIMERA_Cryptographic_Hardware_for_Integrated_Multipurpose_Engine_on_RISC-V_with_ASCON.pdf |
| Exploring the New CV-X-IF Interface to Customize RISC-V Instruction Sets: A Case of Study in Cryptography / Dolmeta, A., Martina, M., Masera, G.. - ELETTRONICO. - 1369:(2025), pp. 39-47. (Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES Torino (Ita) 19-20 September 2024) [10.1007/978-3-031-84100-2_5]. | 1-gen-2025 | Dolmeta, AlessandraMartina, MaurizioMasera, Guido | - |
| Just TestIt! An SBST Approach To Automate System-Integration Testing / Terzano, T., Giuffrida, L., Sapriza, J., Schiavone, P.D., Masera, G., Atienza, D., Lavagno, L., Martina, M.. - (2025), pp. 74-77. (22nd ACM International Conference on Computing Frontiers Cagliari (Ita) May 28–30, 2025) [10.1145/3706594.3726980]. | 1-gen-2025 | Terzano, TommasoGiuffrida, LuigiMasera, GuidoAtienza, DavidLavagno, LucianoMartina, Maurizio + | ACM_OSHW25___TestIt.pdf; 3706594.3726980.pdf |
| Performance Comparison: Software vs. Hardware Implementation of Novel S-Box Designed to Resist Power Analysis Attack / Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 19-27. (Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES Torino (Ita) 19-20 September 2024) [10.1007/978-3-031-84100-2_3]. | 1-gen-2025 | Mirigaldi, MattiaMartina, MaurizioMasera, Guido | Performance_Comparison__Software_vs__Hardware_Implementation_of_Novel_S_Box_Designed_to_Resist_Power_Analysis_Attack.pdf; versione_editoriale_compressed.pdf |
| Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF) / Farnaghinejad, B., Bellizia, D., Dolmeta, A., Masera, G., Porsia, A., Ruospo, A., Di Carlo, S., Savino, A., Sanchez, E.. - (2025), pp. 233-242. (International Test Conference 2025 San Diego, California (USA) September 20-26, 2025) [10.1109/ITC58126.2025.00030]. | 1-gen-2025 | Behnam FarnaghinejadAlessandra DolmetaGuido MaseraAntonio PorsiaAnnachiara RuospoStefano Di CarloAlessandro SavinoErnesto Sanchez + | ITC2025___Power_Side_Channel_Vulnerabilities_of_a_RISC_V_Cryptography_Accelerator_Integrated_into_CVA6_via_CV_X_IF.pdf; Power_Side-Channel_Vulnerabilities_of_a_RISC-V_Cryptography_Accelerator_Integrated_into_CVA6_via_Core-V_eXtension_Interface_CV-X-IF.pdf |
| RISC-V Based Keccak Co-Processor for NIST Post-Quantum Cryptography Standards / Dolmeta, A., Piscopo, V., Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 1-5. (2025 IEEE International Symposium on Circuits and Systems Londra (UK) May 25-28, 2025) [10.1109/iscas56072.2025.11043433]. | 1-gen-2025 | Dolmeta, AlessandraPiscopo, ValeriaMirigaldi, MattiaMartina, MaurizioMasera, Guido | RISC-V_Based_Keccak_Co-Processor_for_NIST_Post-Quantum_Cryptography_Standards.pdf; ISCAS2025 (1).pdf |
| Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes / Caon, M., Chone, C., Schiavone, P.D., Levisse, A., Masera, G., Martina, M., Atienza, D.. - In: IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING. - ISSN 2168-6750. - ELETTRONICO. - 13:3(2025), pp. 1003-1018. [10.1109/TETC.2025.3555869] | 1-gen-2025 | Masera G.Martina M. + | TETC25.pdf; NearMemory_authors.pdf |
| The Quest for Efficient ASCON Implementations: A Comprehensive Review of Implementation Strategies and Challenges / Mirigaldi, M., Piscopo, V., Martina, M., Masera, G.. - In: CHIPS. - ISSN 2674-0729. - ELETTRONICO. - 4:2(2025), pp. 1-29. [10.3390/chips4020015] | 1-gen-2025 | Mirigaldi, MattiaPiscopo, ValeriaMartina, MaurizioMasera, Guido | CHIPS___Ascon_survey.pdf; chips-04-00015-v2.pdf |
| TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems / Ressa, E., Marchisio, A., Martina, M., Masera, G., Shafique, M.. - ELETTRONICO. - (2025), pp. 1-7. (2025 International Joint Conference on Neural Networks (IJCNN) Rome (Ita) 30 giugno - 5 luglio 2025) [10.1109/ijcnn64981.2025.11228478]. | 1-gen-2025 | Martina, MaurizioMasera, Guido + | TinyCL.pdf; IJCNN_25_TinyCL_pdfexpress.pdf |
| TOXOS: Spinning Up Nonlinearity in On-Vehicle Inference with a RISC-V CORDIC Coprocessor / Giuffrida, L., Masera, G., Martina, M.. - In: TECHNOLOGIES. - ISSN 2227-7080. - 13:10(2025). [10.3390/technologies13100479] | 1-gen-2025 | Luigi, GiuffridaGuido, MaseraMaurizio, Martina | technologies-13-00479.pdf |
| TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography / Dolmeta, A., Di Matteo, S., Valea, E., Carmona, M., Loiseau, A., Martina, M., Masera, G.. - ELETTRONICO. - (2025), pp. 1-7. (2025 Design, Automation & Test in Europe Conference (DATE) Lyon (Fra) 31 March - 2 April 2025) [10.23919/date64628.2025.10993202]. | 1-gen-2025 | Dolmeta, AlessandraValea, EmanueleMartina, MaurizioMasera, Guido + | 9_TYRCA_DATE.pdf; TYRCA_A_RISC-V_Tightly-Coupled_Accelerator_for_Code-Based_Cryptography.pdf |
| ATHOS: A Hybrid Accelerator for PQC CRYSTALS-Algorithms exploiting new CV-X-IF Interface / Dolmeta, A., Martina, M., Masera, G.. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 12:(2024), pp. 182340-182352. [10.1109/ACCESS.2024.3511340] | 1-gen-2024 | Alessandra DolmetaMaurizio MartinaGuido Masera | ATHOS_A_Hybrid_Accelerator_for_PQC_CRYSTALS-Algorithms_exploiting_new_CV-X-IF_Interface.pdf |
| Ditching the Queue: Optimizing Coprocessor Utilization with Out-of-Order CPUs on compact Systems on Chip / Caon, M., Masera, G., Martina, M.. - In: ELECTRONICS. - ISSN 2079-9292. - ELETTRONICO. - 13:15(2024). [10.3390/electronics13153018] | 1-gen-2024 | Caon, MicheleMasera, GuidoMartina, Maurizio | Caon-Ditching.pdf |
| Hardware and Software Optimizations for Capsule Networks / Marchisio, A., Bussolino, B., Colucci, A., Mrazek, V., Hanif, M.A., Martina, M., Masera, G., Shafique, M. - In: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing / Pasricha S., Shafique M.. - ELETTRONICO. - [s.l] : Springer, 2024. - ISBN 9783031399312. - pp. 303-328 [10.1007/978-3-031-39932-9_12] | 1-gen-2024 | Martina, MaurizioMasera, Guido + | bussolino_springer_2023.pdf; EmbeddedMLBook_CapsNets_chapter.pdf |
| Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber / Dolmeta, A., Valpreda, E., Martina, M., Masera, G.. - ELETTRONICO. - 1:(2024), pp. 59-62. (Proceedings of the 21st ACM International Conference on Computing Frontiers Workshops and Special Sessions Ischia (Italy) May 7-9, 2024) [10.1145/3637543.3652872]. | 1-gen-2024 | Dolmeta, AlessandraValpreda, EmanueleMartina, MaurizioMasera, Guido | 3637543.3652872.pdf; ACM_OSHW2.pdf |
| LOKI Low-Latency Open-Source Kyber-Accelerator IPs / Dolmeta, A., Mirigaldi, M., Martina, M., Masera, G.. - ELETTRONICO. - 1110:(2024), pp. 29-35. (ApplePies 2023 : International Conference on Applications in Electronics Pervading Industry, Environment and Society Genova, Italy September 28-29, 2023) [10.1007/978-3-031-48121-5_4]. | 1-gen-2024 | Dolmeta, AlessandraMirigaldi, MattiaMartina, MaurizioMasera, Guido | Applepies_2023_preprint.pdf; Masera-LOKI.pdf |