A Multi-Dimensional Design Space Exploration of ChaCha20 on FPGA

The ChaCha20 stream cipher has emerged as a cornerstone of modern network security, particularly within the TLS 1.3 and WireGuard protocols, due to its high performance and inherent resilience against timing-based side-channel attacks. Addressing the lack of holistic trade-off analysis between throughput and area, this paper presents a comprehensive Design Space Exploration (DSE). We propose a modular, highly parameterized FPGA architecture that allows for the systematic modulation of three key dimensions: the level of algorithmic parallelism, the temporal partitioning of operations, and the granularity of the arithmetic datapath. Our experimental analysis on a Xilinx Artix-7 demonstrates a vast performance spectrum, ranging from resource-constrained 8-bit serialized designs to massively unrolled 32-bit architectures. A key finding of this exploration is that extreme datapath slicing (e.g., 8-bit) is counterproductive on modern FPGAs, as the control overhead outweighs the logic savings. Conversely, we identify a sweet-spot configuration that achieves over 2.3 Gb/s while requiring fewer than 700 equivalent slices, corresponding to the best overall efficiency with an area– time product of only 140.33 eSlice x us. The exploration further establishes a minimum-area implementation (507 eSlices) and a minimum-latency architecture (0.059 us), providing practical guidelines for both resource-constrained IoT and high-speed networking applications.