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A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms
2025 Silvano, Cristina; Ielmini, Daniele; Ferrandi, Fabrizio; Fiorin, Leandro; Curzel, Serena; Benini, Luca; Conti, Francesco; Garofalo, Angelo; Zambelli, Cristian; Calore, Enrico; Fabio Schifano, Sebastiano; Palesi, Maurizio; Ascia, Giuseppe; Patti, Davide; Petra, Nicola; De Caro, Davide; Lavagno, Luciano; Urso, Teodoro; Cardellini, Valeria; Carlo Cardarilli, Gian; Birke, Robert; Perri, Stefania
Just TestIt! An SBST Approach To Automate System-Integration Testing
2025 Terzano, Tommaso; Giuffrida, Luigi; Sapriza, Juan; Schiavone, Pasquale Davide; Masera, Guido; Atienza, David; Lavagno, Luciano; Martina, Maurizio
Low-Power Subgraph Isomorphism at the Edge Using FPGAs
2025 Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, Luciano; Pasini, Paolo
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
2025 Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; Lazarescu, Mihai T.; Pasini, Paolo
Comparative Survey of Embedded System Implementations of Convolutional Neural Networks in Autonomous Cars Applications
2024 Cheshfar, Mohammad; Hossein Maghami, Mohammad; Amiri, Parviz; Gharaee Garakani, Hossein; Lavagno, Luciano
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA
2024 Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, Luciano
Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark
2024 Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
2024 Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
2023 Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano
A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis
2023 Jamal, MUHAMMAD USMAN; Li, Zhuowei; Lazarescu, MIHAI T.; Lavagno, Luciano
CUDA-Optimized GPU Acceleration of 3GPP 3D Channel Model Simulations for 5G Network Planning
2023 Shah, NASIR ALI; Lazarescu, Mihai T.; Quasso, Roberto; Lavagno, Luciano
Enhanced Exploration of Neural Network Models for Indoor Human Monitoring
2023 Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T.
Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops
2023 Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
2023 Ottati, Fabrizio; Gao, Chang; Chen, Qinyu; Brignone, Giovanni; Casu, Mario Roberto; Eshraghian, Jason; Lavagno, Luciano.
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs
2022 Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano
Drift Rejection Differential Frontend for Single Plate Capacitive Sensors
2022 Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T.
Fast Energy-Optimal Multi-Kernel DNN-like Application Allocation on Multi-FPGA Platforms
2022 Shan, Junnan; Lazarescu, MIHAI TEODOR; Cortadella, Jordi; Lavagno, Luciano; Casu, MARIO ROBERTO
FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio
2022 Shah, NASIR ALI; Lavagno, Luciano; Lazarescu, Mihai T.; Quasso, Roberto; Scarpina, Salvatore
CNN-on-AWS: Efficient Allocation of Multi-Kernel Applications on Multi-FPGA Platforms
2021 Shan, Junnan; Lazarescu, Mihai T.; Cortadella, Jordi; Lavagno, Luciano; Casu, Mario R.
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs
2021 BIN TARIQ, Osama; Shan, Junnan; Floros, Georgios; Sotiriou, Christos P.; Casu, Mario R.; Lazarescu, MIHAI TEODOR; Lavagno, Luciano
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms / Silvano, Cristina; Ielmini, Daniele; Ferrandi, Fabrizio; Fiorin, Leandro; Curzel, Serena; Benini, Luca; Conti, Francesco; Garofalo, Angelo; Zambelli, Cristian; Calore, Enrico; Fabio Schifano, Sebastiano; Palesi, Maurizio; Ascia, Giuseppe; Patti, Davide; Petra, Nicola; De Caro, Davide; Lavagno, Luciano; Urso, Teodoro; Cardellini, Valeria; Carlo Cardarilli, Gian; Birke, Robert; Perri, Stefania. - In: ACM COMPUTING SURVEYS. - ISSN 0360-0300. - (2025). [10.1145/3729215] | 1-gen-2025 | CRISTINA SILVANOLUCA BENINIFrancesco ContiLuciano LavagnoTeodoro UrsoRobert Birke + | 3729215.pdf |
| Just TestIt! An SBST Approach To Automate System-Integration Testing / Terzano, Tommaso; Giuffrida, Luigi; Sapriza, Juan; Schiavone, Pasquale Davide; Masera, Guido; Atienza, David; Lavagno, Luciano; Martina, Maurizio. - (2025), pp. 74-77. (Intervento presentato al convegno 22nd ACM International Conference on Computing Frontiers tenutosi a Cagliari (Ita) nel May 28–30, 2025) [10.1145/3706594.3726980]. | 1-gen-2025 | Terzano, TommasoGiuffrida, LuigiMasera, GuidoAtienza, DavidLavagno, LucianoMartina, Maurizio + | ACM_OSHW25___TestIt.pdf; 3706594.3726980.pdf |
| Low-Power Subgraph Isomorphism at the Edge Using FPGAs / Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, Luciano; Pasini, Paolo. - In: IEEE ACCESS. - ISSN 2169-3536. - 13:(2025), pp. 67127-67135. [10.1109/ACCESS.2025.3560405] | 1-gen-2025 | Roberto BosioGiovanni BrignoneTeodoro UrsoMihai T. LazarescuLuciano LavagnoPaolo Pasini | Low-Power_Subgraph_Isomorphism_at_the_Edge_Using_FPGAs.pdf |
| NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming / Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; Lazarescu, Mihai T.; Pasini, Paolo. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - 44:5(2025), pp. 1807-1818. [10.1109/tcad.2024.3507570] | 1-gen-2025 | Bosio, RobertoUrso, TeodoroCasu, Mario R.Lavagno, LucianoLazarescu, Mihai T.Pasini, Paolo + | NN2FPGA_Optimizing_CNN_Inference_on_FPGAs_With_Binary_Integer_Programming.pdf; NN2FPGA_Optimizing_CNN_Inference_on_FPGAs_With_Binary_Integer_Programming.pdf |
| Comparative Survey of Embedded System Implementations of Convolutional Neural Networks in Autonomous Cars Applications / Cheshfar, Mohammad; Hossein Maghami, Mohammad; Amiri, Parviz; Gharaee Garakani, Hossein; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - 12:(2024), pp. 182410-182437. [10.1109/ACCESS.2024.3510677] | 1-gen-2024 | Mohammad CheshfarLuciano Lavagno + | Comparative_Survey_of_Embedded_System_Implementations_of_Convolutional_Neural_Networks_in_Autonomous_Cars_Applications.pdf |
| LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA / Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, Luciano. - ELETTRONICO. - (2024), pp. 1-2. (Intervento presentato al convegno 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) tenutosi a Valencia (Spain) nel 25-27 March 2024). | 1-gen-2024 | Bosio RobertoBrignone GiovanniMinnella FilippoMuhammad Usman JamalLavagno Luciano | LESS_extended_abstract.pdf; Bosio-LESS.pdf |
| Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark / Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - STAMPA. - 43:7(2024), pp. 2229-2233. [10.1109/TCAD.2024.3360314] | 1-gen-2024 | Lagostina, LorenzoMinnella, FilippoCortadella, JordiCasu, Mario R.Lazarescu, Mihai T.Lavagno, Luciano | Mix_amp_Latch_Comparison_With_State-of-the-Art_Retiming_On_a_RISC-V_Benchmark.pdf; Minnella-Mix.pdf |
| SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators / Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano. - In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. - ISSN 1936-7406. - (2024). [10.1145/3705324] | 1-gen-2024 | Brignone,GiovanniBosio,RobertoSansoe ClaudioLavagno,Luciano + | SILVIA__Automated_Superword_Level_Parallelism_Exploitation_via_HLS_Specific_LLVM_Passes_for_Compute_Intensive_FPGA_Accelerators.pdf; 3705324.pdf |
| A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs / Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano. - ELETTRONICO. - (2023), pp. 551-557. (Intervento presentato al convegno 2023 IEEE 41st International Conference on Computer Design (ICCD) tenutosi a Washington (USA) nel 06-08 November 2023) [10.1109/ICCD58817.2023.00089]. | 1-gen-2023 | Giovanni BrignoneMihai T. LazarescuLuciano Lavagno | paper.pdf; Brignone-A-DSP.pdf |
| A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis / Jamal, MUHAMMAD USMAN; Li, Zhuowei; Lazarescu, MIHAI T.; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 11:(2023), pp. 85785-85798. [10.1109/ACCESS.2023.3303840] | 1-gen-2023 | MUHAMMAD USMAN JAMALMIHAI T. LAZARESCULUCIANO LAVAGNO + | Lazarescu-AGraph.pdf |
| CUDA-Optimized GPU Acceleration of 3GPP 3D Channel Model Simulations for 5G Network Planning / Shah, NASIR ALI; Lazarescu, Mihai T.; Quasso, Roberto; Lavagno, Luciano. - In: ELECTRONICS. - ISSN 2079-9292. - ELETTRONICO. - 15:(2023). [10.3390/electronics12153214] | 1-gen-2023 | Nasir Ali ShahMihai T. LazarescuLuciano Lavagno + | electronics-12-03214 (1).pdf |
| Enhanced Exploration of Neural Network Models for Indoor Human Monitoring / Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T.. - ELETTRONICO. - (2023), pp. 109-114. (Intervento presentato al convegno 2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI) tenutosi a Monopoli (Bari), Italy nel 08-09 June 2023) [10.1109/IWASI58316.2023.10164436]. | 1-gen-2023 | Subbicini, GiorgiaLavagno, LucianoLazarescu, Mihai T. | Enhanced_Exploration_of_Neural_Network_Models_for_Indoor_Human_Monitoring.pdf; Enhanced Exploration of Neural Network Models for Indoor Human Monitoring(Uploaded).pdf |
| Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops / Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 11:(2023), pp. 1-1. [10.1109/ACCESS.2023.3265809] | 1-gen-2023 | Filippo MinnellaJordi CortadellaMario R. CasuMihai T. LazarescuLuciano Lavagno | Minnella-An Optimization.pdf |
| To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration / Ottati, Fabrizio; Gao, Chang; Chen, Qinyu; Brignone, Giovanni; Casu, Mario Roberto; Eshraghian, Jason; Lavagno, Luciano.. - In: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS. - ISSN 2156-3365. - ELETTRONICO. - 13:4(2023), pp. 1015-1025. [10.1109/JETCAS.2023.3330432] | 1-gen-2023 | Ottati, FabrizioBrignone, GiovanniCasu, Mario RobertoLavagno, Luciano. + | review_jetcas.pdf; Ottati-ToSpike_compressed.pdf |
| Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs / Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 10:(2022), pp. 118858-118877. [10.1109/ACCESS.2022.3219868] | 1-gen-2022 | Brignone, GiovanniJamal, Muhammad UsmanLazarescu, Mihai T.Lavagno, Luciano | ACCESS3219868.pdf; Array-Specific_Dataflow_Caches_for_High-Level_Synthesis_of_Memory-Intensive_Algorithms_on_FPGAs.pdf |
| Drift Rejection Differential Frontend for Single Plate Capacitive Sensors / Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T.. - In: IEEE SENSORS JOURNAL. - ISSN 1530-437X. - ELETTRONICO. - 22:16(2022), pp. 16141-16149. [10.1109/JSEN.2022.3189031] | 1-gen-2022 | Giorgia SubbiciniLuciano LavagnoMihai T. Lazarescu | Drift_Rejection_Differential_Frontend_for_Single_Plate_Capacitive_Sensors.pdf |
| Fast Energy-Optimal Multi-Kernel DNN-like Application Allocation on Multi-FPGA Platforms / Shan, Junnan; Lazarescu, MIHAI TEODOR; Cortadella, Jordi; Lavagno, Luciano; Casu, MARIO ROBERTO. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - ELETTRONICO. - 41:4(2022), pp. 1186-1190. [10.1109/TCAD.2021.3076958] | 1-gen-2022 | Junnan ShanMihai T LazarescuLuciano LavagnoMario Casu + | final.pdf; Lazarescu-Fastenergy.pdf |
| FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio / Shah, NASIR ALI; Lavagno, Luciano; Lazarescu, Mihai T.; Quasso, Roberto; Scarpina, Salvatore. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 10:(2022), pp. 119386-119401. [10.1109/ACCESS.2022.3221124] | 1-gen-2022 | Nasir Ali ShahLuciano LavagnoMihai T. LazarescuSalvatore Scarpina + | FPGA_Acceleration_of_3GPP_Channel_Model_Emulator_for_5G_New_Radio.pdf; Shah-FPGA.pdf |
| CNN-on-AWS: Efficient Allocation of Multi-Kernel Applications on Multi-FPGA Platforms / Shan, Junnan; Lazarescu, Mihai T.; Cortadella, Jordi; Lavagno, Luciano; Casu, Mario R.. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - ELETTRONICO. - 40:2(2021), pp. 301-314. [10.1109/TCAD.2020.2994256] | 1-gen-2021 | Shan, JunnanLazarescu, Mihai T.Lavagno, LucianoCasu, Mario R. + | report.pdf; 09091518.pdf |
| High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs / BIN TARIQ, Osama; Shan, Junnan; Floros, Georgios; Sotiriou, Christos P.; Casu, Mario R.; Lazarescu, MIHAI TEODOR; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 9:(2021), pp. 54286-54297. [10.1109/ACCESS.2021.3067453] | 1-gen-2021 | Osama Bin TariqJunnan ShanMario R. CasuMihai Teodor LazarescuLuciano Lavagno + | 09381853.pdf |