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MINNELLA, FILIPPO
Dipartimento di Elettronica e Telecomunicazioni
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Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark
2024 Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano
Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops
2024 Minnella, Filippo
Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops
2023 Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano
Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory
2022 Minnella, Filippo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark / Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - STAMPA. - (2024), pp. -1. [10.1109/TCAD.2024.3360314] | 1-gen-2024 | Lagostina, LorenzoMinnella, FilippoCortadella, JordiCasu, Mario R.Lazarescu, Mihai T.Lavagno, Luciano | Mix_amp_Latch_Comparison_With_State-of-the-Art_Retiming_On_a_RISC-V_Benchmark.pdf |
| Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops / Minnella, Filippo. - (2024 Mar 18), pp. 1-66. | 18-mar-2024 | MINNELLA, FILIPPO | conv_phd_thesis_filippo_minnella.pdf; conv_abstract.pdf |
| Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops / Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 11:(2023), pp. 1-1. [10.1109/ACCESS.2023.3265809] | 1-gen-2023 | Filippo MinnellaJordi CortadellaMario R. CasuMihai T. LazarescuLuciano Lavagno | Minnella-An Optimization.pdf |
| Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory / Minnella, Filippo. - (2022). | 1-gen-2022 | MINNELLA FILIPPO | US11789078.pdf |