Archivio Istituzionale della RicercaBOSIO, ROBERTO
BOSIO, ROBERTO
Dipartimento di Elettronica e Telecomunicazioni
066485
Low-Power Subgraph Isomorphism at the Edge Using FPGAs
2025 Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, Luciano; Pasini, Paolo
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA
2024 Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, Luciano
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
2024 Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; Lazarescu, Mihai T.; Pasini, Paolo
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
2024 Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Low-Power Subgraph Isomorphism at the Edge Using FPGAs / Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, Luciano; Pasini, Paolo. - In: IEEE ACCESS. - ISSN 2169-3536. - 13:(2025), pp. 67127-67135. [10.1109/ACCESS.2025.3560405] | 1-gen-2025 | Roberto BosioGiovanni BrignoneTeodoro UrsoMihai T. LazarescuLuciano LavagnoPaolo Pasini | Low-Power_Subgraph_Isomorphism_at_the_Edge_Using_FPGAs.pdf |
| LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA / Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, Luciano. - ELETTRONICO. - (2024), pp. 1-2. (Intervento presentato al convegno 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) tenutosi a Valencia (Spain) nel 25-27 March 2024). | 1-gen-2024 | Bosio RobertoBrignone GiovanniMinnella FilippoMuhammad Usman JamalLavagno Luciano | LESS_extended_abstract.pdf; Bosio-LESS.pdf |
| NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming / Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; Lazarescu, Mihai T.; Pasini, Paolo. - In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. - ISSN 0278-0070. - (2024). [10.1109/tcad.2024.3507570] | 1-gen-2024 | Bosio, RobertoUrso, TeodoroCasu, Mario R.Lavagno, LucianoLazarescu, Mihai T.Pasini, Paolo + | NN2FPGA_Optimizing_CNN_Inference_on_FPGAs_With_Binary_Integer_Programming.pdf |
| SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators / Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano. - In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. - ISSN 1936-7406. - (2024). [10.1145/3705324] | 1-gen-2024 | Brignone,GiovanniBosio,RobertoSansoe ClaudioLavagno,Luciano + | SILVIA__Automated_Superword_Level_Parallelism_Exploitation_via_HLS_Specific_LLVM_Passes_for_Compute_Intensive_FPGA_Accelerators.pdf; 3705324.pdf |