Archivio Istituzionale della RicercaBRIGNONE, GIOVANNI
BRIGNONE, GIOVANNI
Dipartimento di Elettronica e Telecomunicazioni
091553
Low-Power Subgraph Isomorphism at the Edge Using FPGAs
2025 Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, Luciano; Pasini, Paolo
Making acceleration more amenable with novel high-level synthesis techniques for FPGAs
2025 Brignone, Giovanni
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
2025 Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA
2024 Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, Luciano
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
2023 Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration
2023 Ottati, Fabrizio; Gao, Chang; Chen, Qinyu; Brignone, Giovanni; Casu, Mario Roberto; Eshraghian, Jason; Lavagno, Luciano.
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs
2022 Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs
2022 Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Low-Power Subgraph Isomorphism at the Edge Using FPGAs / Bosio, R., Brignone, G., Urso, T., Lazarescu, M.T., Lavagno, L., Pasini, P.. - In: IEEE ACCESS. - ISSN 2169-3536. - 13:(2025), pp. 67127-67135. [10.1109/ACCESS.2025.3560405] | 1-gen-2025 | Roberto BosioGiovanni BrignoneTeodoro UrsoMihai T. LazarescuLuciano LavagnoPaolo Pasini | Low-Power_Subgraph_Isomorphism_at_the_Edge_Using_FPGAs.pdf |
| Making acceleration more amenable with novel high-level synthesis techniques for FPGAs / Brignone, Giovanni. - (2025 Jan 22), pp. 1-64. [10.13121/polito/porto/2997456] | 22-gen-2025 | BRIGNONE, GIOVANNI | conv_main-2.pdf; conv_abstract-3.pdf |
| SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators / Brignone, G., Bosio, R., Ottati, F., Sansoe', C., Lavagno, L.. - In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. - ISSN 1936-7406. - 18:2(2025). [10.1145/3705324] | 1-gen-2025 | Brignone,GiovanniBosio,RobertoSansoe ClaudioLavagno,Luciano + | SILVIA__Automated_Superword_Level_Parallelism_Exploitation_via_HLS_Specific_LLVM_Passes_for_Compute_Intensive_FPGA_Accelerators.pdf; 3705324.pdf |
| LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA / Bosio, R., Brignone, G., Minnella, F., Jamal, M.U., Lavagno, L.. - ELETTRONICO. - (2024), pp. 1-2. (2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) Valencia (Spain) 25-27 March 2024). | 1-gen-2024 | Bosio RobertoBrignone GiovanniMinnella FilippoMuhammad Usman JamalLavagno Luciano | LESS_extended_abstract.pdf; Bosio-LESS.pdf |
| A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs / Brignone, G., Lazarescu, M.T., Lavagno, L.. - ELETTRONICO. - (2023), pp. 551-557. (2023 IEEE 41st International Conference on Computer Design (ICCD) Washington (USA) 06-08 November 2023) [10.1109/ICCD58817.2023.00089]. | 1-gen-2023 | Giovanni BrignoneMihai T. LazarescuLuciano Lavagno | paper.pdf; Brignone-A-DSP.pdf |
| To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration / Ottati, F., Gao, C., Chen, Q., Brignone, G., Casu, M.R., Eshraghian, J., Lavagno, Luciano.. - In: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS. - ISSN 2156-3365. - ELETTRONICO. - 13:4(2023), pp. 1015-1025. [10.1109/JETCAS.2023.3330432] | 1-gen-2023 | Ottati, FabrizioBrignone, GiovanniCasu, Mario RobertoLavagno, Luciano. + | review_jetcas.pdf; Ottati-ToSpike_compressed.pdf |
| Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs / Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano. - In: IEEE ACCESS. - ISSN 2169-3536. - ELETTRONICO. - 10:(2022), pp. 118858-118877. [10.1109/ACCESS.2022.3219868] | 1-gen-2022 | Brignone, GiovanniJamal, Muhammad UsmanLazarescu, Mihai T.Lavagno, Luciano | ACCESS3219868.pdf; Array-Specific_Dataflow_Caches_for_High-Level_Synthesis_of_Memory-Intensive_Algorithms_on_FPGAs.pdf |
| Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs / Brignone, G., Jamal, M.U., Lazarescu, M.T., Lavagno, L.. - In: IEEE ACCESS. - ISSN 2169-3536. - 10:(2022), pp. 118858-118877. [10.1109/ACCESS.2022.3219868] | 1-gen-2022 | Brignone, GiovanniJamal, Muhammad UsmanLazarescu, Mihai T.Lavagno, Luciano | - |