Automated Hardware Design Methodology for Digital Filters with High-Level Synthesis

The increasing complexity of digital hardware systems and the demand for faster time-to-market for the semiconductor industry require a rapid and flexible design strategy at an increased abstraction level. To this end, we propose a fully automated hardware design methodology for digital signal processing (DSP) applications such as digital filters, using high-level synthesis (HLS) integrated with MATLAB. This approach enables a one-click workflow from concept design to a synthesized and functionally verified netlist, with the requirement of minimal hardware expertise. After comparison with industry standard register transfer level (RTL) designs of multiple filter architectures, the area of HLS-generated implementations exhibited a variance ranging from a 54.4 % reduction to a 35.8 % overhead. This indicates a comparable quality of results (QoR), especially when weighed against the significant gains in design time reduction and productivity. Beyond digital filters, the work demonstrates that modern HLS tools, when paired with automation and parameterized code, can deliver rapid industrial grade ASIC results, bridging the gap between algorithm development and hardware deployment in digital signal processing and beyond.