Archivio Istituzionale della RicercaMASERA, Guido
MASERA, Guido
Dipartimento di Elettronica e Telecomunicazioni
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Hardware and Software Optimizations for Capsule Networks
2024 Marchisio, Alberto; Bussolino, Beatrice; Colucci, Alessio; Mrazek, Vojtech; Hanif, Muhammad Abdullah; Martina, Maurizio; Masera, Guido; Shafique, Muhammad
Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network
2020 Anzalone, Erik; Capra, Maurizio; Peloso, Riccardo; Martina, Maurizio; Masera, Guido
MP-SoC/NoC Architectures for Error Correction
2015 Condo, Carlo; Martina, Maurizio; Masera, Guido
Hardware Design and Realization for Iteratively Decodable Codes
2014 Emmanuel, Boutillon; Masera, Guido
Enabling “hard” technologies for future wireless
2012 Dominique, Noguet; Marc, Belleville; Dominique, Morche; Gerd, Asheid; Venkatesh, Ramakrishnan; Masera, Guido
VLSI Architectures for WIMAX Channel Decoders
2009 Martina, Maurizio; Masera, Guido
VLSI for turbo codes
2005 Masera, Guido
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization
2003 Addino, M.; Casu, MARIO ROBERTO; Masera, Guido; Piccinini, G.; Zamboni, Maurizio
Effects of Temperature in Deep-Submicron Global Interconnect Optimization
2003 Casu, MARIO ROBERTO; M., Graziano; Masera, Guido; G., Piccinini; Zamboni, Maurizio
A Prolog VLSI System for Real Time Applications
1994 P., Civera; Masera, Guido; RUO ROCH, Massimo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Hardware and Software Optimizations for Capsule Networks / Marchisio, Alberto; Bussolino, Beatrice; Colucci, Alessio; Mrazek, Vojtech; Hanif, Muhammad Abdullah; Martina, Maurizio; Masera, Guido; Shafique, Muhammad - In: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing / Pasricha S., Shafique M.. - ELETTRONICO. - [s.l] : Springer, 2024. - ISBN 9783031399312. - pp. 303-328 [10.1007/978-3-031-39932-9_12] | 1-gen-2024 | Martina, MaurizioMasera, Guido + | bussolino_springer_2023.pdf; EmbeddedMLBook_CapsNets_chapter.pdf |
| Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network / Anzalone, Erik; Capra, Maurizio; Peloso, Riccardo; Martina, Maurizio; Masera, Guido (SMART INNOVATION, SYSTEMS AND TECHNOLOGIES). - In: Progresses in Artificial Intelligence and Neural SystemsELETTRONICO. - [s.l] : Springer, 2020. - ISBN 978-981-15-5092-8. - pp. 79-89 [10.1007/978-981-15-5093-5_8] | 1-gen-2020 | Capra, MaurizioPeloso, RiccardoMartina, MaurizioMasera, Guido + | conv_accel.pdf; Wirn2019_Progresses in Artificial Intelligence and Neural Systems_Capra.pdf |
| MP-SoC/NoC Architectures for Error Correction / Condo, Carlo; Martina, Maurizio; Masera, Guido - In: Advanced Hardware Design for Error Correcting Codes / Cyrille Chavet, Philippe Coussy. - STAMPA. - New York : SPRINGER, 233 SPRING ST, NEW YORK, NY 10013 USA, 2015. - ISBN 9783319105680. - pp. 129-149 [10.1007/978-3-319-10569-7_7] | 1-gen-2015 | CONDO, CARLOMARTINA, MAURIZIOMASERA, Guido | - |
| Hardware Design and Realization for Iteratively Decodable Codes / Emmanuel, Boutillon; Masera, Guido - In: Channel Coding: Theory, Algorithms, and Applications / D. Declerq, C. Fossorier, E. Biglieri. - STAMPA. - Oxford, UK : ACADEMIC PRESS, 2014. - ISBN 9780123964991. - pp. 583-651 | 1-gen-2014 | MASERA, Guido + | - |
| Enabling “hard” technologies for future wireless / Dominique, Noguet; Marc, Belleville; Dominique, Morche; Gerd, Asheid; Venkatesh, Ramakrishnan; Masera, Guido - In: The Newcom++ Vision Book / S. Benedetto, L.M. Correia, M. Luise. - ELETTRONICO. - Milano : Springer-Verlag, 2012. - ISBN 9788847019829. - pp. 145-167 [10.1007/978-88-470-1983-6_8] | 1-gen-2012 | MASERA, Guido + | - |
| VLSI Architectures for WIMAX Channel Decoders / Martina, Maurizio; Masera, Guido - In: WIMAX, New DevelopmentsSTAMPA. - VUKOVATAR : Upena, Dalal, Kosta, 2009. - ISBN 9789537619534. - pp. 107-132 | 1-gen-2009 | MARTINA, MAURIZIOMASERA, Guido | 1.pdf |
| VLSI for turbo codes / Masera, Guido - In: Turbo Code Applications: a journey from a paper to realization / KEATTISAK SRIPIMANWAT. - [s.l], 2005. - ISBN 9781402036866. | 1-gen-2005 | MASERA, Guido | - |
| A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization / Addino, M.; Casu, MARIO ROBERTO; Masera, Guido; Piccinini, G.; Zamboni, Maurizio - In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation / J.J. CHICO AND E. MACII EDS. - STAMPA. - BERLIN : Springer-Verlag, 2003. - ISBN 9783540200741. - pp. 121-130 (( convegno PATMOS 2002 [10.1007/978-3-540-39762-5_14]. | 1-gen-2003 | CASU, MARIO ROBERTOMASERA, GuidoG. PICCININIZAMBONI, Maurizio + | patmos02_addino.pdf |
| Effects of Temperature in Deep-Submicron Global Interconnect Optimization / Casu, MARIO ROBERTO; M., Graziano; Masera, Guido; G., Piccinini; Zamboni, Maurizio - In: Lecture Notes in Computer Science, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation / J.J. CHICO AND E. MACII EDS.. - Berlin : Springer Publisher, 2003. - ISBN 9783540200741. - pp. 90-100 | 1-gen-2003 | CASU, MARIO ROBERTOM. GrazianoMASERA, GuidoZAMBONI, Maurizio + | - |
| A Prolog VLSI System for Real Time Applications / P., Civera; Masera, Guido; RUO ROCH, Massimo - In: VLSI for Neural Networks andArtificial Intelligence / J.G. DELGADO-FRIAS AND W.R. MOORE. - NEW YORK : Plenum Press, 1994. - ISBN 9780306447228. - pp. 285-296 | 1-gen-1994 | MASERA, GuidoRUO ROCH, Massimo + | - |