Archivio Istituzionale della RicercaA method for SoC global interconnect characterization is presented. Buses are partitioned in blocks whose electrical characterization is done using reduced size primitives and extending the results to the original structure. The accuracy is measured on typical metrics like delays, crosstalk peaks and reabsorbing time. This work is the basis for an automatic evaluator of interconnect metrics to be used in SoC design space explorations and verification.
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization / Addino, M.; Casu, MARIO ROBERTO; Masera, Guido; Piccinini, G.; Zamboni, Maurizio - In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation / J.J. CHICO AND E. MACII EDS. - STAMPA. - BERLIN : Springer-Verlag, 2003. - ISBN 9783540200741. - pp. 121-130 (( convegno PATMOS 2002 [10.1007/978-3-540-39762-5_14].
A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization
CASU, MARIO ROBERTO;MASERA, Guido;G. PICCININI;ZAMBONI, Maurizio
2003
Abstract
A method for SoC global interconnect characterization is presented. Buses are partitioned in blocks whose electrical characterization is done using reduced size primitives and extending the results to the original structure. The accuracy is measured on typical metrics like delays, crosstalk peaks and reabsorbing time. This work is the basis for an automatic evaluator of interconnect metrics to be used in SoC design space explorations and verification.
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https://hdl.handle.net/11583/1854135
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