MP-SoC/NoC Architectures for Error Correction

Error Correcting Codes (ECCs) have gained noteworthy attention in the last years, mainly due to the development of new standards for high throughput communications, either for wireless or wired terminals. Such high throughput can be achieved by the means of optimized hardware architectures and, in the last ten years, several efforts have been spent to address implementation aspects that are recognized as challenging issues. One of the milestones in today hardware architectures for high throughput ECC decoding is to design parallel architectures, where the decoder relies on several processing elements. In order to support different ECCs or even different standards, processing elements have to be flexible and the interconnection backbone must be easily reconfigured to meet the characteristics and the parameters of the decoding algorithms. Recent studies show that interesting results, to cope with these problems, can be achieved by bringing the Multi-Processor-System-on-Chip (MP-SoC) and Network-on-Chip (NoC) paradigms into decoder architecture design. Basically, the MP-SoC and NoC approaches have been developed to facilitate the design of complex systems made of heterogeneous units, which often are specific Intellectual Property (IP) cores. We refer to this case as inter-IP MP-SoCs and inter-IP NoCs. On the other hand, the ECC decoder, although composed of multiple properly interconnected processing elements, still is one individual IP core in a complex SoC transceiver. As a consequence, we refer to MP-SoC and NoC approaches applied to the specific case of ECC as intra-IP MP-SoCs and intra-IP NoCs, respectively.This chapter will first analyze the key requirements of modern channel decoders, like very high degree of parallelism, introduced at different levels, and large flexibility with respect to supported codes, at the same time. The different kinds of flexibility that can be demanded in current and future communication systems are then introduced and the key requirements of multi-standard decoders are briefly discussed, with particular emphasis on versatile communication structures used to connect processing elements. Both direct and indirect networks are studied as possible supports for flexible interconnect needs. The effects of different choices in terms of network topology, routing and scheduling algorithm, buffer size, and processing element micro-architecture are also studied. Finally, the critical issue of dynamically switching between heterogeneous standards and communication modes is explored.