Archivio Istituzionale della RicercaSANCHEZ SANCHEZ, EDGAR ERNESTO
SANCHEZ SANCHEZ, EDGAR ERNESTO
Dipartimento di Automatica e Informatica
Sanchez, Ernesto; E. Sanchez; Sanchez E.; Ernesto Sanchez; SANCHEZ EDGAR; SANCHEZ E.; SANCHEZ SANCHEZ EDGAR ERNESTO; SANCHEZ SANCHEZ E.
012684
A Benchmark Suite of RT-level Hardware Trojansfor Pipelined Microprocessor Cores
2021 Damljanovic, Aleksa; Ruospo, Annachiara; Sanchez Sanchez, Ernesto; Squillero, Giovanni
A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC
2017 Bernardi, Paolo; Appello, Davide; Giacopelli, Giampaolo; Motta, Alessandro; Pagani, Alberto; Pollaccia, Giorgio; Rabbi, Christian; Restifo, Marco; Ruberg, Priit; Sanchez, Ernesto; Villa, Claudio Maria; Venini, Federico
A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips
2019 Floridia, Andrea; Piumatti, Davide; Ruospo, Annachiara; Ernesto, Sanchez; Sergio De Luca, ; Rosario, Martorana
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
2009 Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller
2017 Bernardi, Paolo; Cantoro, Riccardo; Gianotto, L.; Restifo, Marco; SANCHEZ SANCHEZ, EDGAR ERNESTO; Venini, Federico; Appello, D.
A fault grading methodology for software-based self-test programs in systems-on-chip
2010 Ballan, O.; Bernardi, Paolo; Fontana, G.; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO
A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks
2019 Portolan, Michele; Cantoro, Riccardo; Ernesto, Sanchez
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
2011 M., Valka; A., Bosio; L., Dilillo; P., Girard; S., Pravossoudovitch; A., Virazel; SANCHEZ SANCHEZ, EDGAR ERNESTO; DE CARVALHO, Mauricio; SONZA REORDA, Matteo
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors
2013 Bernardi, Paolo; Du, Boyang; Ciganda, LYL MERCEDES; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Grosso, Michelangelo; Ballan, O.
A hardware accelerated framework for the generation of design validation programs for SMT processors
2010 SANCHEZ SANCHEZ, EDGAR ERNESTO; Danilo, Ravotto; SONZA REORDA, Matteo
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
2008 PEREZ W., J; VELASCO MEDINA, J; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo
A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs
2021 Floridia, Andrea; Sanchez Sanchez, Ernesto
A local analysis of an incremental evolutionary tool for processor diagnosis
2007 Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni
A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
2004 SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; Violante, Massimo
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications
2021 Matana Luza, Lucas; Ruospo, Annachiara; Bosio, Alberto; Ernesto, Sanchez; Dilillo, Luigi
A modular Architecture for a Populationless Evolutionary Algorithm for MIP
2005 SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni
A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
2008 Christou, K; MICHAEL M., K; Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo
A Pipelined Multi-Level Fault Injector for Deep Neural Networks
2020 Ruospo, Annachiara; Balaara, Angelo; Bosio, Alberto; Ernesto, Sanchez
A reliability analysis of a deep neural network
2019 Bosio, A.; Bernardi, P.; Ruospo, A.; Sanchez, E.
A SBST strategy to test microprocessors' branch target buffer
2012 Bernardi, Paolo; Ciganda, LYL MERCEDES; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| A Benchmark Suite of RT-level Hardware Trojansfor Pipelined Microprocessor Cores / Damljanovic, Aleksa; Ruospo, Annachiara; Sanchez Sanchez, Ernesto; Squillero, Giovanni. - ELETTRONICO. - (2021). ((Intervento presentato al convegno 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) tenutosi a Vienna, Austria nel April 7-9. | 1-gen-2021 | Damljanovic, AleksaRuospo, AnnachiaraSanchez Sanchez, ErnestoSquillero, Giovanni | Trojan2021_DDECS_.pdf |
| A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC / Bernardi, Paolo; Appello, Davide; Giacopelli, Giampaolo; Motta, Alessandro; Pagani, Alberto; Pollaccia, Giorgio; Rabbi, Christian; Restifo, Marco; Ruberg, Priit; Sanchez, Ernesto; Villa, Claudio Maria; Venini, Federico. - (2017). ((Intervento presentato al convegno Design, Automation and Test in Europe Conference and Exhibition (DATE2017). | 1-gen-2017 | BERNARDI, PAOLORESTIFO, MARCOSanchez, ErnestoVENINI, FEDERICO + | - |
| A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips / Floridia, Andrea; Piumatti, Davide; Ruospo, Annachiara; Ernesto, Sanchez; Sergio De Luca, ; Rosario, Martorana. - ELETTRONICO. - (2019), pp. 1-10. ((Intervento presentato al convegno 2019 IEEE International Test Conference (ITC) tenutosi a Washington (USA) nel 9 - 15 November, 2019 [10.1109/ITC44170.2019.9000129]. | 1-gen-2019 | Andrea FloridiaDavide PiumattiRUOSPO, ANNACHIARAErnesto Sanchez + | pre_print_IEEE.pdf; post_print_IEEE.pdf |
| A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores / Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2009), pp. 103-108. ((Intervento presentato al convegno 9th International Workshop on Microprocessor Test and Verification (MTV'08) tenutosi a Austin, TX (U.S.A.) nel 8-10 Dic., 2008 [10.1109/MTV.2008.9]. | 1-gen-2009 | BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo | - |
| A DMA and CACHE-based stress schema for burn-in of automotive microcontroller / Bernardi, Paolo; Cantoro, Riccardo; Gianotto, L.; Restifo, Marco; SANCHEZ SANCHEZ, EDGAR ERNESTO; Venini, Federico; Appello, D.. - STAMPA. - (2017), pp. 1-6. ((Intervento presentato al convegno 2017 18th IEEE Latin American Test Symposium (LATS) tenutosi a Bogota (CO) nel 13-15 March 2017 [10.1109/LATW.2017.7906767]. | 1-gen-2017 | BERNARDI, PAOLOCANTORO, RICCARDORESTIFO, MARCOSANCHEZ SANCHEZ, EDGAR ERNESTOVENINI, FEDERICO + | PUBLISHED_07906767.pdf |
| A fault grading methodology for software-based self-test programs in systems-on-chip / Ballan, O.; Bernardi, Paolo; Fontana, G.; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO. - (2010), pp. 43-46. ((Intervento presentato al convegno International Workshop on Microprocessor Test and Verification tenutosi a Austin (TX), USA nel Dec. 13-15, 2010 [10.1109/MTV.2010.16]. | 1-gen-2010 | BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTO + | - |
| A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks / Portolan, Michele; Cantoro, Riccardo; Ernesto, Sanchez. - ELETTRONICO. - (2019), pp. 1-2. ((Intervento presentato al convegno 2019 IEEE European Test Symposium (ETS) tenutosi a Baden-Baden, Germany nel 27-31 May 2019 [10.1109/ETS.2019.8791522]. | 1-gen-2019 | Michele PortolanRiccardo CantoroErnesto Sanchez | CAMERA_READY-ets19-38.pdf; PUBLISHED-08791522.pdf |
| A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing / M., Valka; A., Bosio; L., Dilillo; P., Girard; S., Pravossoudovitch; A., Virazel; SANCHEZ SANCHEZ, EDGAR ERNESTO; DE CARVALHO, Mauricio; SONZA REORDA, Matteo. - (2011), pp. 153-158. ((Intervento presentato al convegno 2011 16th IEEE European Test Symposium (ETS) [10.1109/ETS.2011.21]. | 1-gen-2011 | SANCHEZ SANCHEZ, EDGAR ERNESTODE CARVALHO, MAURICIOSONZA REORDA, Matteo + | - |
| A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors / Bernardi, Paolo; Du, Boyang; Ciganda, LYL MERCEDES; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Grosso, Michelangelo; Ballan, O.. - STAMPA. - (2013). ((Intervento presentato al convegno IEEE 7th International Design and Test Symposium (IDT) tenutosi a Doha (Qatar) nel December 2012 [10.1109/IDT.2013.6727120]. | 1-gen-2013 | BERNARDI, PAOLODU, BOYANGCIGANDA, LYL MERCEDESSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, MatteoGROSSO, MICHELANGELO + | 06727120.pdf |
| A hardware accelerated framework for the generation of design validation programs for SMT processors / SANCHEZ SANCHEZ, EDGAR ERNESTO; Danilo, Ravotto; SONZA REORDA, Matteo. - (2010). ((Intervento presentato al convegno 13th IEEE International Symposium on Design & Diagnostics of Elctronic Circuits and Systems tenutosi a Vienna, Austria nel April 2010. | 1-gen-2010 | SANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + | - |
| A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs / PEREZ W., J; VELASCO MEDINA, J; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2008), pp. 143-148. ((Intervento presentato al convegno IOLTS 2008: IEEE International On-line Testing Symposium. | 1-gen-2008 | RAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + | - |
| A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs / Floridia, Andrea; Sanchez Sanchez, Ernesto. - ELETTRONICO. - 2021 12th IEEE Latin America Symposium on Circuits and System:(2021), pp. 1-4. ((Intervento presentato al convegno 12th IEEE Latin America Symposium on Circuits and System tenutosi a Arequipa (Perú) nel February 21-25, 2021. | 1-gen-2021 | Floridia, AndreaSanchez Sanchez, Ernesto | A_JTAG-based_Fault_Emulation_Platform_for_Dependability_Analyses_of_Processor-based_ASICs.pdf |
| A local analysis of an incremental evolutionary tool for processor diagnosis / Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni. - (2007), pp. 3467-3473. ((Intervento presentato al convegno IEEE Congress on Evolutionary Computation, 2007. CEC 2007 tenutosi a Singapore nel 25-28 Sept. 2007 [10.1109/CEC.2007.4424921]. | 1-gen-2007 | RAVOTTO, DANILOSANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSQUILLERO, Giovanni | 1648932.pdf |
| A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems / SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; Violante, Massimo. - (2004), pp. 871-878. ((Intervento presentato al convegno Congress on Evolutionary Computation [10.1109/CEC.2004.1330952]. | 1-gen-2004 | SANCHEZ SANCHEZ, EDGAR ERNESTOSQUILLERO, GiovanniVIOLANTE, MASSIMO | - |
| A Model-Based Framework to Assess the Reliability of Safety-Critical Applications / Matana Luza, Lucas; Ruospo, Annachiara; Bosio, Alberto; Ernesto, Sanchez; Dilillo, Luigi. - ELETTRONICO. - (2021), pp. 41-44. ((Intervento presentato al convegno 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) tenutosi a Vienna, Austria nel 7-9 April 2021 [10.1109/DDECS52668.2021.9417059]. | 1-gen-2021 | Annachiara RuospoErnesto Sanchez + | 2021_DDECS___preprint.pdf; 09417059_postprint.pdf |
| A modular Architecture for a Populationless Evolutionary Algorithm for MIP / SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni. - (2005). ((Intervento presentato al convegno GSICE05: Giornata di Studio Italiana sul Calcolo Evolutivo tenutosi a Milano nel September 20 2005. | 1-gen-2005 | SANCHEZ SANCHEZ, EDGAR ERNESTOSCHILLACI, MASSIMILIANOSQUILLERO, Giovanni | - |
| A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm / Christou, K; MICHAEL M., K; Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2008), pp. 389-394. ((Intervento presentato al convegno 26th IEEE VLSI Test Symposium tenutosi a San Diego, CA, USA nel apr 27 - may 1 [10.1109/VTS.2008.37]. | 1-gen-2008 | BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + | - |
| A Pipelined Multi-Level Fault Injector for Deep Neural Networks / Ruospo, Annachiara; Balaara, Angelo; Bosio, Alberto; Ernesto, Sanchez. - ELETTRONICO. - (2020). ((Intervento presentato al convegno IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) tenutosi a ESA-ESRIN, Frascati (Rome) Italy nel October 19 – October 21, 2020 [10.1109/DFT50435.2020.9250866]. | 1-gen-2020 | Annachiara RuospoAngelo BalaaraAlberto BosioErnesto Sanchez | DFT_2020_CR_FINAL.pdf |
| A reliability analysis of a deep neural network / Bosio, A.; Bernardi, P.; Ruospo, A.; Sanchez, E.. - (2019), pp. 1-6. ((Intervento presentato al convegno 20th IEEE Latin American Test Symposium, LATS 2019 tenutosi a Santiago del Chile nel 2019 [10.1109/LATW.2019.8704548]. | 1-gen-2019 | Bernardi P.Ruospo A.Sanchez E. + | - |
| A SBST strategy to test microprocessors' branch target buffer / Bernardi, Paolo; Ciganda, LYL MERCEDES; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - STAMPA. - (2012), pp. 306-311. ((Intervento presentato al convegno IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2012) tenutosi a Tallinn, Estonia nel April 18-20, 2012. | 1-gen-2012 | BERNARDI, PAOLOCIGANDA, LYL MERCEDESGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo | - |