System on Chip devices include an increasing number of embedded memory cores, whose test during the operational phase is often a strict requirement, especially for safety-critical applications. This paper proposes a new memory test method combining the characteristics of hardware and software solutions: the test is performed by the microcontroller/processor, while the code of the test instructions to be executed is generated on-the-fly by an ad hoc module, also in charge of checking the memory behavior. The solution is modular and does not require any modification either in the memory cores or in the processor. Moreover, it is well suited to be used for test during the operational phase. Experimental results, gathered by implementing some representative March elements and algorithms, show that the method guarantees higher defect coverage than software BIST and a test time comparable with that of traditional hardware BIST solutions with a reduced hardware cost.

An efficient method for the test of embedded memory cores during the operational phase / Bernardi, Paolo; Ciganda, LYL MERCEDES; SONZA REORDA, Matteo; Hamdioui, Said. - STAMPA. - (2013), pp. 227-232. ((Intervento presentato al convegno 2013 22nd Asian Test Symposium tenutosi a Yilan, Taiwan nel Nov. 2013.

An efficient method for the test of embedded memory cores during the operational phase

BERNARDI, PAOLO;CIGANDA, LYL MERCEDES;SONZA REORDA, Matteo;HAMDIOUI, SAID
2013

Abstract

System on Chip devices include an increasing number of embedded memory cores, whose test during the operational phase is often a strict requirement, especially for safety-critical applications. This paper proposes a new memory test method combining the characteristics of hardware and software solutions: the test is performed by the microcontroller/processor, while the code of the test instructions to be executed is generated on-the-fly by an ad hoc module, also in charge of checking the memory behavior. The solution is modular and does not require any modification either in the memory cores or in the processor. Moreover, it is well suited to be used for test during the operational phase. Experimental results, gathered by implementing some representative March elements and algorithms, show that the method guarantees higher defect coverage than software BIST and a test time comparable with that of traditional hardware BIST solutions with a reduced hardware cost.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2520897
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