An effective ATPG flow for Gate Delay Faults

This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition Delay Faults, a traditional ATPG procedure can be used to determine patterns without any explicit timing information. The latter may account for several iterations, and it is returning the minimum delay that is detected for each delay faults. Effectiveness and feasibility of the proposed ATPG flow have been demonstrated on ISCAS’89 and ITC’99 benchmarks.