Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.
A new hybrid fault detection technique for systems-on-a-chip / BERNARDI P.; VEIRAS BOLZANI LM.; M.REBAUDENGO; M.SONZA REORDA; F.L.VARGAS; M.VIOLANTE. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 55(2006), pp. 185-198.
|Titolo:||A new hybrid fault detection technique for systems-on-a-chip|
|Data di pubblicazione:||2006|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/TC.2006.15|
|Appare nelle tipologie:||1.1 Articolo in rivista|