Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided.

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller / Bernardi, Paolo; Cantoro, Riccardo; Gianotto, L.; Restifo, Marco; SANCHEZ SANCHEZ, EDGAR ERNESTO; Venini, Federico; Appello, D.. - STAMPA. - (2017), pp. 1-6. ((Intervento presentato al convegno 2017 18th IEEE Latin American Test Symposium (LATS) tenutosi a Bogota (CO) nel 13-15 March 2017 [10.1109/LATW.2017.7906767].

A DMA and CACHE-based stress schema for burn-in of automotive microcontroller

BERNARDI, PAOLO;CANTORO, RICCARDO;RESTIFO, MARCO;SANCHEZ SANCHEZ, EDGAR ERNESTO;VENINI, FEDERICO;
2017

Abstract

Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2669875
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