PORTO @ Archivio Istituzionale della Ricerca

PRINETTO, Paolo Ernesto
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
EU - Europa 127.232
NA - Nord America 44.435
AS - Asia 7.090
AF - Africa 265
SA - Sud America 212
OC - Oceania 21
Continente sconosciuto - Info sul continente non disponibili 12
Totale 179.267
Salva come PNG Salva come JPEG
Nazione #
IT - Italia 92.450
US - Stati Uniti d'America 44.168
GB - Regno Unito 9.705
FR - Francia 9.285
DE - Germania 6.832
CN - Cina 2.896
UA - Ucraina 2.304
RU - Federazione Russa 1.666
NL - Olanda 1.420
TR - Turchia 1.131
SG - Singapore 990
KR - Corea 746
IE - Irlanda 744
SE - Svezia 662
CH - Svizzera 456
FI - Finlandia 408
IN - India 261
CA - Canada 245
PK - Pakistan 199
BE - Belgio 193
AT - Austria 164
ID - Indonesia 145
JO - Giordania 143
JP - Giappone 143
PL - Polonia 121
RO - Romania 114
ZA - Sudafrica 113
HK - Hong Kong 106
BG - Bulgaria 105
IR - Iran 93
MY - Malesia 91
ES - Italia 84
VE - Venezuela 83
EU - Europa 78
VN - Vietnam 66
SN - Senegal 64
CL - Cile 56
AP - ???statistics.table.value.countryCode.AP??? 54
TW - Taiwan 54
BR - Brasile 48
CZ - Repubblica Ceca 37
IL - Israele 35
SI - Slovenia 34
DK - Danimarca 32
GR - Grecia 31
EG - Egitto 27
SK - Slovacchia (Repubblica Slovacca) 27
EE - Estonia 23
PT - Portogallo 22
BY - Bielorussia 20
TH - Thailandia 18
MD - Moldavia 17
AR - Argentina 16
AE - Emirati Arabi Uniti 13
AU - Australia 13
HR - Croazia 13
DZ - Algeria 11
MX - Messico 10
NG - Nigeria 10
GH - Ghana 9
KZ - Kazakistan 9
AZ - Azerbaigian 8
HU - Ungheria 8
LT - Lituania 8
LU - Lussemburgo 8
PH - Filippine 8
TN - Tunisia 8
MA - Marocco 7
NO - Norvegia 7
NZ - Nuova Zelanda 7
AL - Albania 6
CI - Costa d'Avorio 5
CO - Colombia 5
GT - Guatemala 5
LV - Lettonia 5
SA - Arabia Saudita 5
ET - Etiopia 4
KE - Kenya 4
PS - Palestinian Territory 4
SY - Repubblica araba siriana 4
AM - Armenia 3
CR - Costa Rica 3
PA - Panama 3
GE - Georgia 2
MT - Malta 2
PE - Perù 2
QA - Qatar 2
SC - Seychelles 2
UY - Uruguay 2
UZ - Uzbekistan 2
BD - Bangladesh 1
BH - Bahrain 1
CY - Cipro 1
IM - Isola di Man 1
IQ - Iraq 1
KG - Kirghizistan 1
KW - Kuwait 1
LK - Sri Lanka 1
MO - Macao, regione amministrativa speciale della Cina 1
PR - Porto Rico 1
Totale 179.262
Salva come PNG Salva come JPEG
Città #
Torino 82.729
Ashburn 10.765
Southend 8.987
Seattle 5.009
Fairfield 3.803
Woodbridge 1.870
Turin 1.769
Houston 1.558
Chandler 1.530
Cambridge 1.417
Wilmington 1.324
Boardman 1.300
Des Moines 1.263
Jacksonville 1.101
Ann Arbor 1.075
Princeton 1.041
Milan 968
Buffalo 937
Izmir 714
Singapore 709
Dublin 694
San Ramon 676
Berlin 631
Saint Petersburg 627
Herkenbosch 600
Shanghai 566
San Francisco 563
Chicago 562
Zhengzhou 500
Hangzhou 456
Beijing 447
Bern 415
Helsinki 384
San Donato Milanese 371
San Jose 301
Zaporozhye 279
Pennsylvania Furnace 275
Baltimore 268
Amsterdam 261
Santa Clara 252
Istanbul 229
Monopoli 223
Mountain View 222
Overberg 218
New York 202
Norwalk 194
Las Vegas 186
San Diego 185
Dallas 173
Rome 173
Vienna 144
Frankfurt 141
Jakarta 140
Padua 139
Fremont 138
University Park 138
Borgaro Torinese 134
Council Bluffs 132
Redwood City 131
Brussels 125
Malatya 111
Paris 106
Moscow 103
Indiana 102
Muizenberg 102
Guangzhou 99
Seoul 95
Austin 94
Phoenix 92
Ottawa 89
Bologna 88
Clearwater 86
Falls Church 83
Seongnam 83
Melun 82
Dearborn 81
London 81
La Jolla 76
Shenzhen 75
Lecce 72
Toronto 65
Henderson 62
Los Angeles 60
Verona 60
Caracas 58
Galati 56
Andover 55
Cedar Rapids 53
Kornik 53
Dong Ket 52
Washington 52
Atlanta 51
Nürnberg 50
Naples 49
Bremen 47
Nanjing 45
Riva 44
Alba 43
Lviv 40
Osaka 40
Totale 145.199
Salva come PNG Salva come JPEG
Nome #
Genetic Defect Based March Test Generation for SRAM 1.157
"Plug & Test" at System Level via Testable TLM Primitives 993
On-line testing of an off-the-shelf microprocessor board for safety-critical applications 931
A Web Based Platform for Sign Language Corpus Creation 915
The use of model checking in ATPG for sequential circuits 885
Reti Logiche (Esercizi commentati e risolti) 881
Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures 872
An area-efficient 2-D convolution implementation on FPGA for space applications 848
Control-flow checking via regular expressions 844
SEU effect analysis in a open-source router via a distributed fault injection environment 829
FAUST: fault-injection script-based tool 826
Software-Based Self-Test of Set-Associative Cache Memories 824
An On-line BIST RAM Architecture with Self Repair Capabilities 816
A cloud-based Cyber-Physical System for environmental monitoring 808
EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards 803
AIDI: An adaptive image denoising FPGA-based IP-core for real-time applications 797
A programmable BIST architecture for clusters of Multiple-Port SRAMs 796
Single-Event Upset Analysis and Protection in High Speed Circuits 795
Static analysis of SEU effects on software applications 792
On integrating a proprietary and a commercial architecture for optimal BIST performances in SoCs 792
ABLUR: An FPGA-based adaptive deblurring core for real-time applications 788
An optimal algorithm for the automatic generation of March tests 787
Validation of a software dependability tool via fault injection experiments 786
A PVM tool for automatic test generation on parallel and distributed systems 782
Data criticality estimation in software applications 781
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs 780
Design and Optimization of Adaptable BCH Codecs for NAND Flash Memories 780
Automating the IEEE std. 1500 compliance verification for embedded cores 780
March AB, March AB1: new March tests for unlinked dynamic memory faults 777
FLARE: A design environment for FLASH-based space applications 777
March Test Generation Revealed 771
Software dependability techniques validated via fault injection experiments 770
Ef3S: An evaluation framework for flash-based systems 763
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems 760
A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits 760
Online and Offline BIST in IP-Core Design 758
SAFE: a Self Adaptive Frame Enhancer FPGA-based IP-core for real-time space applications 758
Flash-memories in Space Applications: Trends and Challenges 757
Applying March Tests to K-Way Set-Associative Cache Memories 756
Testing Embedded Memories in Telecommunication Systems 755
An effective distributed BIST architecture for RAMs 754
Test engineering education in Europe: the EuNICE-Test project 754
A watchdog processor to detect data and control flow errors 752
ATPG for Dynamic Burn-In Test in Full-Scan Circuits 752
Design Issues and Challenges of File Systems for Flash Memories 750
IEEE Standard 1500 Compliance Verification for Embedded Cores 750
A methodology for system-level design for verifiability 745
Microprocessor fault-tolerance via on-the-fly partial reconfiguration 743
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs 738
SSDExplorer: a Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives 735
System Level Testing via TLM 2.0 Debug Transport Interface 732
Digital, memory and mixed-signal test engineering education: five centres of competence in Europe 731
Automatic March tests generation for static and dynamic faults in SRAMs 729
Memory read faults: taxonomy and automatic test generation 727
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers 726
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches 725
Exploiting competing subpopulations for automatic generation of test sequences for digital circuits 725
Using ER Models for Microprocessor Functional Test Coverage Evaluation 725
Online self-repair of FIR filters 724
NBTI Mitigation by Dynamic Partial Reconfiguration 724
ZipStream: improving dependability in Dynamic Partial Reconfiguration 722
A novel methodology to increase fault tolerance in autonomous FPGA-based systems 721
Increasing the robustness of CUDA Fermi GPU-based systems 720
On applying the set covering model to reseeding 719
Language Resources for Computer Assisted Translation from Italian to Italian Sign Language of Deaf People 718
Integrating MultiWordNet with Italian Sign Language lexical resources 717
Test exploration and validation using transaction level models 713
Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells 712
Memory Fault Simulator for Static-Linked Faults 712
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC 712
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories 710
DFT and BIST of a multichip module for high-energy physics experiments 709
A software-based self test of CUDA Fermi GPUs 707
Automatic March tests generation for multi-port SRAMs 706
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications 706
A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures 705
SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives 704
A 22n March Test for Realistic Static Linked Faults in SRAMs 701
March AB, a State-of-the-Art March Test for Realistic Static Linked Faults and Dynamic Faults in SRAMs 700
A Self-Repairing Execution Unit for Microprogrammed Processors 700
Automated Synthesis of SEU Tolerant Architectures from OO Descriptions 700
EDACs and test integration strategies for NAND flash memories 698
Power-aware voltage tuning for STT-MRAM reliability 695
Fault mitigation strategies for CUDA GPUs 693
Efficient Multi-level Fault Simulation of HW/SW Systems for Structural Faults 686
Automatic March Tests Generations for Static Linked Faults in SRAMs 684
TLM 2.0 simple sockets synthesis to RTL 684
Specification and design of a new memory fault simulator 682
Automating defects simulation and fault modeling for SRAMs 673
A Low-Cost FPGA-Based Test and Diagnosis Architecture for SRAMs 670
Integration of STT-MRAM model into CACTI simulator 669
Test infrastructures evaluation at transaction level 667
Side-channel analysis of SEcube™ platform 667
A unifying formalism to support automated synthesis of SBSTs for embedded caches 667
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems 663
Towards microagent based DBIST/DBISR 662
Defective Behaviour of an 8T SRAM Cell with Open Defects 662
FLARES: an aging aware algorithm to autonomously adapt the error correction capability in NAND Flash memories 661
A Fault Injection Methodology and Infrastructure for Fast Single Event Upsets Emulation on Xilinx SRAM-based FPGAs 660
A novel algorithm and hardware architecture for fast video-based shape reconstruction of space debris 658
Totale 75.086
Salva come PNG Salva come JPEG
Categoria #
all - tutte 314.075
article - articoli 59.721
book - libri 4.404
conference - conferenze 246.768
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.182
Totale 628.150
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20207.620 0 0 0 0 1.384 1.352 1.087 1.322 1.319 565 361 230
2020/20218.973 868 1.085 521 1.491 1.155 1.090 405 562 389 657 439 311
2021/20226.020 250 460 176 494 298 669 550 356 339 530 988 910
2022/20237.557 608 952 281 664 712 838 1.460 311 661 100 373 597
2023/20242.320 157 177 119 178 255 397 105 145 74 116 279 318
2024/20253.185 306 1.173 376 993 337 0 0 0 0 0 0 0
Totale 180.166