This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing
A programmable BIST architecture for clusters of Multiple-Port SRAMs / Benso, Alfredo; DI CARLO, Stefano; DI NATALE, Giorgio; Prinetto, Paolo Ernesto; Lobetti Bodoni, M.. - STAMPA. - (2000), pp. 557-566. ((Intervento presentato al convegno IEEE International Test Conference (ITC) tenutosi a Atlantic City (NJ), USA nel 3-5 Oct. 2000 [10.1109/TEST.2000.894249].
Titolo: | A programmable BIST architecture for clusters of Multiple-Port SRAMs | |
Autori: | ||
Data di pubblicazione: | 2000 | |
Abstract: | This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a... set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing | |
ISBN: | 0780365461 | |
Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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File | Descrizione | Tipologia | Licenza | |
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2000-ITC-RAM BIST-AuthorVersion.pdf | Manuscript author version | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
2000-ITC-RAM BIST.pdf | Published version | 2. Post-print / Author's Accepted Manuscript | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/1500007