The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a single BIST processor, implemented as a microprogrammable machine and able to execute different test algorithms, a wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST processor. Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.

An effective distributed BIST architecture for RAMs / Benso, Alfredo; Chiusano, SILVIA ANNA; DI CARLO, Stefano; DI NATALE, Giorgio; LOBETTI BODONI, M.; Prinetto, Paolo Ernesto. - STAMPA. - (2000), pp. 119-124. ((Intervento presentato al convegno IEEE European Test Workshop (ETW) tenutosi a Cascais, PT nel 23-26 May 2000 [10.1109/ETW.2000.873788].

An effective distributed BIST architecture for RAMs

BENSO, Alfredo;CHIUSANO, SILVIA ANNA;DI CARLO, STEFANO;DI NATALE, Giorgio;PRINETTO, Paolo Ernesto
2000

Abstract

The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a single BIST processor, implemented as a microprogrammable machine and able to execute different test algorithms, a wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST processor. Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/1499844
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