With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cost.
"Plug & Test" at System Level via Testable TLM Primitives / Alemzadeh, H.; DI CARLO, Stefano; Refan, F.; Navabi, Z.; Prinetto, Paolo Ernesto. - STAMPA. - (2008), pp. 1-10. (Intervento presentato al convegno IEEE International Test Conference (ITC) tenutosi a Santa Clara (CA), USA nel 28-30 Oct., 2008) [10.1109/TEST.2008.4700610].
"Plug & Test" at System Level via Testable TLM Primitives
DI CARLO, STEFANO;PRINETTO, Paolo Ernesto
2008
Abstract
With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cost.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/1801700
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