This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip.
A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures / Benso, Alfredo; Cataldo, Silvia; Chiusano, SILVIA ANNA; Prinetto, Paolo Ernesto; Zorian, Y.. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - STAMPA. - 16:3(2000), pp. 179-184. [10.1023/A:1008326928340]
A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures
BENSO, Alfredo;CATALDO, Silvia;CHIUSANO, SILVIA ANNA;PRINETTO, Paolo Ernesto;
2000
Abstract
This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip.File | Dimensione | Formato | |
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2000-JETTA-EDA-BIST-AuthorVersion.pdf
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https://hdl.handle.net/11583/1404460
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