Working at system level is attracting increasing interest. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial cases.

A methodology for system-level design for verifiability / Camurati, Paolo Enrico; Corno, Fulvio; Prinetto, Paolo Ernesto. - STAMPA. - 683:(1993), pp. 80-91. ((Intervento presentato al convegno IFIPWG10.2 Advanced Research Working Conference, CHARME'93 tenutosi a Arles (FRA) nel May 24–26, 1993 [10.1007/BFb0021716].

A methodology for system-level design for verifiability

CAMURATI, Paolo Enrico;CORNO, Fulvio;PRINETTO, Paolo Ernesto
1993

Abstract

Working at system level is attracting increasing interest. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial cases.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2374692
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