This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance graceful degradation by executing in software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened. The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform it. As proof of concept a design using this idea has been developed, using the LEON3 open-source processor, synthesized on a Virtex 4 FPGA.

Microprocessor fault-tolerance via on-the-fly partial reconfiguration / DI CARLO, Stefano; Miele, Andrea; Prinetto, Paolo Ernesto; Trapanese, Antonio. - STAMPA. - (2010), pp. 201-206. ((Intervento presentato al convegno IEEE 15th European Test Symposium (ETS) tenutosi a Praga, CZ nel 24-28 May 2010 [10.1109/ETSYM.2010.5512759].

Microprocessor fault-tolerance via on-the-fly partial reconfiguration

DI CARLO, STEFANO;MIELE, ANDREA;PRINETTO, Paolo Ernesto;TRAPANESE, ANTONIO
2010

Abstract

This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance graceful degradation by executing in software the tasks that were executed in hardware before a fault and the subsequent reconfiguration happened. The advantage of the proposed approach is that thanks to a hardware hypervisor, the CPU is totally unaware of the reconfiguration happening in real-time, and there's no dependency on the CPU to perform it. As proof of concept a design using this idea has been developed, using the LEON3 open-source processor, synthesized on a Virtex 4 FPGA.
9781424458349
File in questo prodotto:
File Dimensione Formato  
2010-ETS-DPR.pdf

accesso aperto

Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 295.97 kB
Formato Adobe PDF
295.97 kB Adobe PDF Visualizza/Apri
2010-ETS-DPR-AuthorVersion.pdf

accesso aperto

Descrizione: Manuscript author version
Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 7.41 MB
Formato Adobe PDF
7.41 MB Adobe PDF Visualizza/Apri
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2380367
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo