The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes of realistic functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure. The proposed method exploits the capabilities of evolutionary algorithms to automatically identify faulty behaviors into defective memories and to define the corresponding fault models and relevant test sequences. Target defects are modeled at the electrical level in order to optimize the results to the specific technology and memory architecture.
Automating defects simulation and fault modeling for SRAMs / DI CARLO, Stefano; Prinetto, Paolo Ernesto; Scionti, A.; Al Ars, Z.. - STAMPA. - (2008), pp. 169-176. (Intervento presentato al convegno IEEE International High Level Design Validation and Test Workshop (HLDVT) tenutosi a The Hyatt Regency Lake Tahoe Resort (NE), USA nel 19-21 Nov. 2008) [10.1109/HLDVT.2008.4695898].
Automating defects simulation and fault modeling for SRAMs
DI CARLO, STEFANO;PRINETTO, Paolo Ernesto;
2008
Abstract
The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes of realistic functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure. The proposed method exploits the capabilities of evolutionary algorithms to automatically identify faulty behaviors into defective memories and to define the corresponding fault models and relevant test sequences. Target defects are modeled at the electrical level in order to optimize the results to the specific technology and memory architecture.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/1844475
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