Archivio Istituzionale della RicercaFPGAs achieve smaller geometries and their reliability is becoming a severe issue. Non-functional prop- erties, as Negative Bias Temperature Instability, affect the device functionality. In this work a novel methodology to address this issue is described, exploiting FPGAs flexibility. Dynamic Partial Reconfiguration is used to minimize aging impact on FPGAs’ configuration memory.
NBTI Mitigation by Dynamic Partial Reconfiguration / DI CARLO, Stefano; Galfano, Salvatore; Gambardella, Giulio; Indaco, Marco; Prinetto, Paolo Ernesto; Rolfo, Daniele; Trotta, Pascal. - STAMPA. - (2012), pp. 93-96. (Intervento presentato al convegno IEEE 13th Biennal Baltic Electronics Conference (BEC) tenutosi a Tallin, EE nel 03-05 Oct., 2012) [10.1109/BEC.2012.6376823].
NBTI Mitigation by Dynamic Partial Reconfiguration
DI CARLO, STEFANO;GALFANO, SALVATORE;GAMBARDELLA, GIULIO;INDACO, MARCO;PRINETTO, Paolo Ernesto;ROLFO, DANIELE;TROTTA, PASCAL
2012
Abstract
FPGAs achieve smaller geometries and their reliability is becoming a severe issue. Non-functional prop- erties, as Negative Bias Temperature Instability, affect the device functionality. In this work a novel methodology to address this issue is described, exploiting FPGAs flexibility. Dynamic Partial Reconfiguration is used to minimize aging impact on FPGAs’ configuration memory.
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https://hdl.handle.net/11583/2503788
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