The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flop.
Single-Event Upset Analysis and Protection in High Speed Circuits / Hosseinabady, M.; Lofti Kamran, P.; DI NATALE, Giorgio; DI CARLO, Stefano; Benso, Alfredo; Prinetto, Paolo Ernesto. - STAMPA. - (2006), pp. 29-34. (Intervento presentato al convegno IEEE 11th European Test Symposium (ETS) tenutosi a SouthAmpton (UK) nel 21-24 May 2006) [10.1109/ETS.2006.41].
Single-Event Upset Analysis and Protection in High Speed Circuits
DI NATALE, Giorgio;DI CARLO, STEFANO;BENSO, Alfredo;PRINETTO, Paolo Ernesto
2006
Abstract
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flop.File | Dimensione | Formato | |
---|---|---|---|
2006-ETS-SEU.pdf
accesso aperto
Tipologia:
2. Post-print / Author's Accepted Manuscript
Licenza:
Pubblico - Tutti i diritti riservati
Dimensione
261.29 kB
Formato
Adobe PDF
|
261.29 kB | Adobe PDF | Visualizza/Apri |
2006-ETS-SEU-AuthorVersion.pdf
accesso aperto
Descrizione: Manuscript author version
Tipologia:
2. Post-print / Author's Accepted Manuscript
Licenza:
Pubblico - Tutti i diritti riservati
Dimensione
8.01 MB
Formato
Adobe PDF
|
8.01 MB | Adobe PDF | Visualizza/Apri |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/1499972
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo