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EnglishSome design environments may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structure-oriented techniques are the state-of-the-art, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach.
The use of model checking in ATPG for sequential circuits / P. Camurati; M. Gilli; P. Prinetto; M. Sonza Reorda. - 531(1991), pp. 86-95. ((Intervento presentato al convegno Computer-Aided Verification 2nd International Conference, CAV '90 tenutosi a New Brunswick, NJ (USA) nel June 18-21, 1990.
| Titolo: | The use of model checking in ATPG for sequential circuits | |
| Autori: | ||
| Data di pubblicazione: | 1991 | |
| Rivista: | ||
| Abstract: | Some design environments may prevent Design for Testability techniques from reducing testing to a... combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structure-oriented techniques are the state-of-the-art, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach. | |
| ISBN: | 3540544771 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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