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EnglishThis paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.
| Titolo: | Specification and design of a new memory fault simulator |
| Autori: | |
| Data di pubblicazione: | 2002 |
| Abstract: | This paper presents a new fault simulator architecture for RAM memories. The key features of the ...proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints. |
| ISBN: | 0769518257 |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| 2002-ATS-RASTA-1.pdf | 2. Post-print | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia | |
| 2002-ATS-RASTA-AuthorVersion.pdf | Manuscript author version | 2. Post-print | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
http://hdl.handle.net/11583/1499906
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