This paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.
Specification and design of a new memory fault simulator / Benso, Alfredo; DI CARLO, Stefano; DI NATALE, Giorgio; Prinetto, Paolo Ernesto. - STAMPA. - (2002), pp. 92-97. ((Intervento presentato al convegno IEEE 11th AsianTest Symposium (ATS) tenutosi a Guam, USA nel 18-20 Nov. 2002 [10.1109/ATS.2002.1181693].
Titolo: | Specification and design of a new memory fault simulator | |
Autori: | ||
Data di pubblicazione: | 2002 | |
Abstract: | This paper presents a new fault simulator architecture for RAM memories. The key features of the ...proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints. | |
ISBN: | 0769518257 | |
Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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http://hdl.handle.net/11583/1499906