Modern SRAM-based Field Programmable Gate Ar- rays (FPGAs) are increasingly employed in safety- and mission- critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. As- sessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated in- frastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.

A Fault Injection Methodology and Infrastructure for Fast Single Event Upsets Emulation on Xilinx SRAM-based FPGAs / DI CARLO, Stefano; Prinetto, Paolo Ernesto; Rolfo, D.; Trotta, P.. - ELETTRONICO. - (2014), pp. 159-164. ((Intervento presentato al convegno 27th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium (DFTS) tenutosi a Amsterdam, NL nel 1-3 Oct. 2014 [10.1109/DFT.2014.6962073].

A Fault Injection Methodology and Infrastructure for Fast Single Event Upsets Emulation on Xilinx SRAM-based FPGAs

DI CARLO, STEFANO;PRINETTO, Paolo Ernesto;
2014

Abstract

Modern SRAM-based Field Programmable Gate Ar- rays (FPGAs) are increasingly employed in safety- and mission- critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. As- sessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated in- frastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2571947
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