SONZA REORDA, MATTEO

SONZA REORDA, MATTEO  

Dipartimento di Automatica e Informatica  

REORDA M. S; Reorda, Matteo Sonza; Reorda M. Sonza; M. Sonza Reorda; Reorda, M. S.; M.S. Reorda; Matteo Sonza Reorda  

001894  

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Citazione Data di pubblicazione Autori File
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D., Appello; A., Fudoli; V., Tancorre; Corno, Fulvio; Rebaudengo, Maurizio; SONZA REORDA, Matteo. - (2002), pp. 112-116. ((Intervento presentato al convegno IOLTW2002: IEEE International On-line Testing Workshop tenutosi a Isola di Bendor, Francia nel 8-10 luglio 2002. 1-gen-2002 CORNO, FulvioREBAUDENGO, MaurizioSONZA REORDA, Matteo + -
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques / D., Appello; A., Fudoli; V., Tancorre; Bernardi, Paolo; Corno, Fulvio; Rebaudengo, Maurizio; SONZA REORDA, Matteo. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - 20:(2004), pp. 79-87. [10.1023/B:JETT.0000009315.57771.94] 1-gen-2004 BERNARDI, PAOLOCORNO, FulvioREBAUDENGO, MaurizioSONZA REORDA, Matteo + -
A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture / Rebaudengo, Maurizio; SONZA REORDA, Matteo. - 1067:(1996), pp. 987-988. ((Intervento presentato al convegno High-Performance Computing and Networking International Conference and Exhibition HPCN EUROPE 1996 tenutosi a Brussels (BEL) nel April 15–19, 1996 [10.1007/3-540-61142-8_675]. 1-gen-1996 REBAUDENGO, MaurizioSONZA REORDA, Matteo -
A Compaction Method for STLs for GPU in-field test / Guerrero-Balaguera, Juan-David; Rodriguez Condia, J. E.; Sonza Reorda, M.. - ELETTRONICO. - (2022), pp. 454-459. ((Intervento presentato al convegno 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 tenutosi a Antwerp (BE) nel 14-23 March 2022 [10.23919/DATE54114.2022.9774597]. 1-gen-2022 Guerrero-Balaguera Juan-DavidRodriguez Condia J. E.Sonza Reorda M. A_Compaction_Method_for_STLs_for_GPU_in-field_test.pdf
A comparative overview of ATPG flows targeting traditional and cell-aware fault models / Mirabella, Nunzio; Floridia, Andrea; Cantoro, Riccardo; Grosso, Michelangelo; Sonza Reorda, Matteo. - ELETTRONICO. - (In corso di stampa), pp. 1-4. ((Intervento presentato al convegno 29th IEEE International Conference on Electronics Circuits and Systems (ICECS) tenutosi a Glasgow nel 24th - 26th October 2022. In corso di stampa Mirabella, NunzioFloridia, AndreaCantoro, RiccardoGrosso, MichelangeloSonza Reorda, Matteo ICECS_2022_1.2.pdfConference_paper_1.2_submitted.docx
A Data Parallel Algorithm for Boolean Function Manipulation / Gai, Silvano; Rebaudengo, Maurizio; SONZA REORDA, Matteo. - (1995), pp. 28-34. ((Intervento presentato al convegno Frontiers of Massively Parallel Computation, 1995. Proceedings. Frontiers '95., Fifth Symposium on the tenutosi a McLean, VA, USA nel 6-9 Feb 1995 [10.1109/FMPC.1995.380467]. 1-gen-1995 GAI, SilvanoREBAUDENGO, MaurizioSONZA REORDA, Matteo -
A data parallel approach to Boolean function manipulation using BDDs / Cabodi, Gianpiero; Gai, Silvano; Rebaudengo, Maurizio; SONZA REORDA, Matteo. - (1994), pp. 163-175. ((Intervento presentato al convegno Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on tenutosi a Ischia (I) nel 2-6 May 1994 [10.1109/MPCS.1994.367081]. 1-gen-1994 CABODI, GianpieroGAI, SilvanoREBAUDENGO, MaurizioSONZA REORDA, Matteo -
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores / Bernardi, Paolo; Grosso, Michelangelo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - (2009), pp. 103-108. ((Intervento presentato al convegno 9th International Workshop on Microprocessor Test and Verification (MTV'08) tenutosi a Austin, TX (U.S.A.) nel 8-10 Dic., 2008 [10.1109/MTV.2008.9]. 1-gen-2009 BERNARDI, PAOLOGROSSO, MICHELANGELOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo -
A diagnostic test pattern generation algorithm / Camurati, Paolo Enrico; Medina, D.; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo. - (1990), pp. 52-58. ((Intervento presentato al convegno ITC 1990: IEEE International Test Conference 1990 tenutosi a Washington DC (USA) nel 10-14 Sept. 1990 [10.1109/TEST.1990.114000]. 1-gen-1990 CAMURATI, Paolo EnricoPRINETTO, Paolo ErnestoSONZA REORDA, Matteo + -
A dynamic greedy test scheduler for optimizing probe motion in in-circuit testers / Bonaria, L.; Raganato, M.; Sonza Reorda, M.; Squillero, G.. - STAMPA. - 2019-:(2019), pp. 1-2. ((Intervento presentato al convegno 2019 IEEE European Test Symposium, ETS 2019 tenutosi a Baden Baden, Germany nel 2019 [10.1109/ETS.2019.8791519]. 1-gen-2019 Sonza Reorda M.Squillero G. + 08791519 pre print.pdfA_Dynamic_Greedy_Test_Scheduler_for_Optimizing_Probe_Motion_in_In-Circuit_Testers.pdf
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs / Rodriguez Condia, Josie E.; Narducci, Pierpaolo; Reorda, M. Sonza; Sterpone, L.. - ELETTRONICO. - (2020), pp. 1-6. ((Intervento presentato al convegno 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) tenutosi a Novi Sad, Serbia, Serbia nel 22-24 April 2020 [10.1109/DDECS50862.2020.9095665]. 1-gen-2020 Rodriguez Condia, Josie E.Reorda, M. SonzaSterpone, L. + 09095665.pdf
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs / Rodriguez Condia, Josie E.; Narducci, Pierpaolo; Reorda, M. Sonza; Sterpone, L.. - ELETTRONICO. - (2020), pp. 1-6. ((Intervento presentato al convegno 2020 IEEE 38th VLSI Test Symposium (VTS) tenutosi a San Diego, USA nel 5-8 April 2020 [10.1109/VTS48691.2020.9107572]. 1-gen-2020 Rodriguez Condia, Josie E.Reorda, M. SonzaSterpone, L. + 09107572.pdf
A Fault Injection Environment for Microprocessor-based Board / Benso, Alfredo; Prinetto, Paolo Ernesto; Rebaudengo, Maurizio; SONZA REORDA, Matteo. - STAMPA. - (1998), pp. 768-773. ((Intervento presentato al convegno IEEE International Test Conference (ITC) tenutosi a Washington (DC), USA nel 18-23 Oct. 1998 [10.1109/TEST.1998.743259]. 1-gen-1998 BENSO, AlfredoPRINETTO, Paolo ErnestoREBAUDENGO, MaurizioSONZA REORDA, Matteo 1998-ITC-FaultInjection-uP.pdf
A Fault Injection Environment for SoPC's Embedded Microprocessors / M., PORTELA GARCIA; Sterpone, Luca; C., LOPEZ ONGIL; SONZA REORDA, Matteo; Violante, Massimo. - (2006), pp. 68-73. ((Intervento presentato al convegno 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina. 1-gen-2006 STERPONE, LucaSONZA REORDA, MatteoVIOLANTE, MASSIMO + -
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors / Mohammadi, Hassan Ghasemzadeh; Gaillardon, Pierre Emmanuel; Zhang, Jian; Micheli, Giovanni De; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - In: ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS. - ISSN 1550-4832. - STAMPA. - 13:2(2017), pp. 1-13. [10.1145/2988234] 1-gen-2017 SANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo + a16-mohammadi.pdf
A Flexible Framework for the Automatic Generation of SBST Programs / Riefert, Andreas; Cantoro, Riccardo; Sauer, Matthias; SONZA REORDA, Matteo; Becker, Bernd. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - STAMPA. - (2016), pp. 1-12. [10.1109/TVLSI.2016.2538800] 1-gen-2016 CANTORO, RICCARDOSONZA REORDA, Matteo + preprint.pdf07440859.pdf
A Functional Approach for Testing the Reorder Buffer Memory / DI CARLO, Stefano; Gaudesi, Marco; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - STAMPA. - 30:4(2014), pp. 469-481. [10.1007/s10836-014-5461-9] 1-gen-2014 DI CARLO, STEFANOGAUDESI, MARCOSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, Matteo 2014-JETTA-ROB.pdf2014-JETTA-ROB-AuthorVersion.pdf
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing / M., Valka; A., Bosio; L., Dilillo; P., Girard; S., Pravossoudovitch; A., Virazel; SANCHEZ SANCHEZ, EDGAR ERNESTO; DE CARVALHO, Mauricio; SONZA REORDA, Matteo. - (2011), pp. 153-158. ((Intervento presentato al convegno 2011 16th IEEE European Test Symposium (ETS) [10.1109/ETS.2011.21]. 1-gen-2011 SANCHEZ SANCHEZ, EDGAR ERNESTODE CARVALHO, MAURICIOSONZA REORDA, Matteo + -
A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors / Bernardi, Paolo; Du, Boyang; Ciganda, LYL MERCEDES; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Grosso, Michelangelo; Ballan, O.. - STAMPA. - (2013). ((Intervento presentato al convegno IEEE 7th International Design and Test Symposium (IDT) tenutosi a Doha (Qatar) nel December 2012 [10.1109/IDT.2013.6727120]. 1-gen-2013 BERNARDI, PAOLODU, BOYANGCIGANDA, LYL MERCEDESSANCHEZ SANCHEZ, EDGAR ERNESTOSONZA REORDA, MatteoGROSSO, MICHELANGELO + 06727120.pdf
A genetic algorithm for automatic generation of test logic for digital circuits / Corno, Fulvio; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo;  ,. - STAMPA. - (1996), pp. 10-16. ((Intervento presentato al convegno ICTAI 1996 : 8th IEEE International Conference on Tools with Artificial Intelligence, 1996 tenutosi a Toulouse (France) nel Nov 16-19, 1996 [10.1109/TAI.1996.560394]. 1-gen-1996 CORNO, FulvioPRINETTO, Paolo ErnestoSONZA REORDA, Matteo + -