Advances in technology nodes, activity stress caused by data-intensive workloads, and harsh operating conditions increase the occurrence of faults in edge devices used in Artificial Intelligence domains, severely impacting their reliability. Among diverse accelerators, Vector Processing Units (VPUs) offer a versatile and flexible architecture for accelerating workload execution by exploiting data-level parallelism. This paper targets fault detection for VPUs and describes a method for generating Software Test Libraries (STLs) to detect permanent faults arising during the in-field operational phase. The method generates an STL for the baseline accelerator and customizes it for any VPU configuration. The STL for the baseline VPU configuration is built by first exploiting application code, identifying suitable data patterns to improve fault detectability, and then adding a few Ad Hoc routines. The resulting test, once the target hardware parameters are known, is customized using the proposed framework to ensure its effectiveness on the final VPU. The time constraints of in-field tests are taken into account by minimizing the test duration. The experimental results, obtained on a configurable VPU for edge AI applications (Klessydra-T), show that our framework supports the development of effective STLs (up to 96% stuck-at Fault Coverage (FC) for large size configurations). Remarkably, we observed that using a generic STL without accounting for the specific hardware configuration can cause an FC drop of about 25%, highlighting the need for a framework that automatically customizes the test to the VPU’s parameters. The framework is particularly attractive for scalable devices where long-term reliability is essential, and tests must be designed for different hardware configurations.

A Flexible Framework for Vector Accelerators In-field Testing / Vilar De Farias, G., Rodriguez Condia, J.E., Sonza Reorda, M.. - (2026). (44th IEEE VLSI Test Symposium Napa, CA (USA) 27-29 April 2026) [10.1109/VTS69484.2026.11563325].

A Flexible Framework for Vector Accelerators In-field Testing

Gustavo, Vilar de Farias;Josie Esteban, Rodriguez Condia;Matteo, Sonza Reorda
2026

Abstract

Advances in technology nodes, activity stress caused by data-intensive workloads, and harsh operating conditions increase the occurrence of faults in edge devices used in Artificial Intelligence domains, severely impacting their reliability. Among diverse accelerators, Vector Processing Units (VPUs) offer a versatile and flexible architecture for accelerating workload execution by exploiting data-level parallelism. This paper targets fault detection for VPUs and describes a method for generating Software Test Libraries (STLs) to detect permanent faults arising during the in-field operational phase. The method generates an STL for the baseline accelerator and customizes it for any VPU configuration. The STL for the baseline VPU configuration is built by first exploiting application code, identifying suitable data patterns to improve fault detectability, and then adding a few Ad Hoc routines. The resulting test, once the target hardware parameters are known, is customized using the proposed framework to ensure its effectiveness on the final VPU. The time constraints of in-field tests are taken into account by minimizing the test duration. The experimental results, obtained on a configurable VPU for edge AI applications (Klessydra-T), show that our framework supports the development of effective STLs (up to 96% stuck-at Fault Coverage (FC) for large size configurations). Remarkably, we observed that using a generic STL without accounting for the specific hardware configuration can cause an FC drop of about 25%, highlighting the need for a framework that automatically customizes the test to the VPU’s parameters. The framework is particularly attractive for scalable devices where long-term reliability is essential, and tests must be designed for different hardware configurations.
2026
979-8-3315-6337-0
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/3007196