Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation

A fault list analysis methodology is proposed to determine how many Cell-Aware Test (CAT) defects can be detected by test patterns generated targeting the other fault models, including stuck-at faults (SAFs), transition-delay faults(TDFs), and small-delay defects (SDDs). Our analysis reveals that a proper ordering in fault simulation can accelerate the CAT fault simulation process. We evaluated our approach on a RISC-V core, synthesized using an industrial technology library. We demonstrated an innovative method to optimize CAT fault simulation by means of preliminary static fault list analysis, resulting in fault simulation runtime reduction of up to 80% for static and 35% for dynamic CAT faults.