PORTO @ Archivio Istituzionale della Ricerca

SONZA REORDA, MATTEO
 Distribuzione geografica
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Continente #
EU - Europa 92.441
NA - Nord America 64.618
AS - Asia 13.189
SA - Sud America 349
AF - Africa 283
OC - Oceania 40
Continente sconosciuto - Info sul continente non disponibili 29
Totale 170.949
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Nazione #
US - Stati Uniti d'America 63.968
IT - Italia 37.977
GB - Regno Unito 14.378
FR - Francia 12.262
DE - Germania 11.449
CN - Cina 6.146
RU - Federazione Russa 3.849
UA - Ucraina 3.613
SG - Singapore 2.158
NL - Olanda 1.965
TR - Turchia 1.779
IE - Irlanda 1.202
SE - Svezia 1.120
CH - Svizzera 938
KR - Corea 872
FI - Finlandia 642
CA - Canada 620
LT - Lituania 513
PL - Polonia 461
BE - Belgio 453
JP - Giappone 432
IN - India 421
HK - Hong Kong 286
JO - Giordania 279
PK - Pakistan 263
AT - Austria 255
ID - Indonesia 170
BG - Bulgaria 165
BR - Brasile 158
RO - Romania 150
EU - Europa 128
EE - Estonia 126
SN - Senegal 114
ES - Italia 108
IR - Iran 103
MY - Malesia 96
GR - Grecia 90
AP - ???statistics.table.value.countryCode.AP??? 86
TW - Taiwan 69
DK - Danimarca 61
IL - Israele 57
CO - Colombia 48
VN - Vietnam 47
CL - Cile 46
CZ - Repubblica Ceca 46
AE - Emirati Arabi Uniti 44
PT - Portogallo 41
TH - Thailandia 38
AU - Australia 36
BY - Bielorussia 34
MD - Moldavia 32
EG - Egitto 31
BO - Bolivia 30
UY - Uruguay 30
PH - Filippine 25
ZA - Sudafrica 25
GH - Ghana 23
AM - Armenia 22
SK - Slovacchia (Repubblica Slovacca) 21
NG - Nigeria 20
MA - Marocco 19
NO - Norvegia 16
VE - Venezuela 16
HR - Croazia 15
MX - Messico 15
LU - Lussemburgo 14
DZ - Algeria 13
HU - Ungheria 13
CI - Costa d'Avorio 12
KZ - Kazakistan 12
PE - Perù 12
RS - Serbia 12
SA - Arabia Saudita 12
GT - Guatemala 11
SC - Seychelles 11
SI - Slovenia 11
CY - Cipro 10
AR - Argentina 8
AL - Albania 7
MK - Macedonia 7
IQ - Iraq 5
TN - Tunisia 5
UZ - Uzbekistan 5
BD - Bangladesh 4
LK - Sri Lanka 4
MT - Malta 4
NZ - Nuova Zelanda 4
QA - Qatar 4
A2 - ???statistics.table.value.countryCode.A2??? 3
AZ - Azerbaigian 3
BA - Bosnia-Erzegovina 3
BH - Bahrain 3
GE - Georgia 3
LV - Lettonia 3
MM - Myanmar 3
MO - Macao, regione amministrativa speciale della Cina 3
AO - Angola 2
ET - Etiopia 2
MU - Mauritius 2
PS - Palestinian Territory 2
Totale 170.934
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Città #
Torino 25.248
Ashburn 17.473
Southend 13.245
Seattle 7.338
Fairfield 4.925
Chandler 2.756
Turin 2.756
Woodbridge 2.496
Houston 2.160
Boardman 2.097
Princeton 1.912
Cambridge 1.894
Zhengzhou 1.806
Jacksonville 1.748
Wilmington 1.651
Santa Clara 1.557
Singapore 1.524
Ann Arbor 1.499
Hangzhou 1.266
Saint Petersburg 1.216
Berlin 1.145
Dublin 1.145
Des Moines 1.060
Izmir 1.036
Milan 948
San Ramon 879
Bern 837
Beijing 744
Chicago 705
Shanghai 694
San Donato Milanese 654
Helsinki 586
Herkenbosch 546
Council Bluffs 491
Zaporozhye 470
Bologna 452
Istanbul 439
Baltimore 428
Pennsylvania Furnace 426
Mountain View 425
Brussels 396
Overberg 394
Monopoli 372
Kraków 317
New York 298
San Diego 275
Amsterdam 265
Padua 255
Vienna 241
Waterloo 231
Frankfurt 214
Malatya 194
Lecce 187
Fremont 186
Redwood City 179
Rotterdam 169
Rome 167
Moscow 163
San Francisco 162
Guangzhou 151
Buffalo 150
Toronto 145
Shenzhen 143
Jakarta 141
London 137
La Jolla 136
Dearborn 132
Melun 125
Bremen 123
Cedar Rapids 118
Frankfurt am Main 118
Paris 118
Kwai Chung 112
Ottawa 110
Norwalk 108
Seoul 94
Las Vegas 93
Tallinn 90
Putian 87
Washington 84
Falls Church 81
Kornik 81
Atlanta 79
Andover 78
Overland Park 75
Stuttgart 75
Dallas 70
Kansas City 70
Osaka 70
Yubileyny 70
Aubervilliers 68
Modena 66
Valfenera 63
Kiev 61
Verona 60
Ningbo 58
Redmond 56
Fuzhou 53
Columbus 52
Penza 49
Totale 119.192
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Nome #
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms 1.519
On-line testing of an off-the-shelf microprocessor board for safety-critical applications 934
The use of model checking in ATPG for sequential circuits 887
EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards 806
A PVM tool for automatic test generation on parallel and distributed systems 785
On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors 775
FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems 766
A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits 764
A Functional Approach for Testing the Reorder Buffer Memory 733
Exploiting competing subpopulations for automatic generation of test sequences for digital circuits 728
La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti 724
E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services 663
TPDL*: Extended Temporal Profile Description Language 655
Simulation-Based Verification of Network Protocols Performance 652
A Fault Injection Environment for Microprocessor-based Board 637
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits 636
An extended model to support detailed GPGPU reliability analysis 628
GATTO: A Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits 621
Il ruolo delle tecniche di fault injection nell’analisi dell’affidabilità dei sistemi 619
A low cost programmable board for speeding-upfault-injection in Microprocessor based systems 613
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits 604
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG 585
Cellular automata for deterministic sequential test pattern generation 582
Fault Behavior Observation of a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment 582
An Approach to Sequential Circuit Diagnosis Based on Formal Verification Techniques 581
Expressing logical and temporal conditions in simulation environments: TPDL* 580
A Hybrid Fault Injection Methodology for Real Time Systems 576
C_TPDL* : adapting TPDL* to concurrent simulation environments 573
A diagnostic test pattern generation algorithm 569
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information 567
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization 565
An integrated HW and SW fault injection environment for real-time systems 564
A new model for improving symbolic Product Machine traversal 562
Guaranteeing Testability in Re-encoding for Low Power. 562
Fault Injection for Embedded Microprocessor-based Systems 560
Sequential circuit diagnosis based on formal verification techniques 556
Model Checking and Graph Theory in sequential ATPG 555
An experimental comparison of different approaches to ROM BIST 554
Initializability Analysis of Synchronous Sequential Circuits 553
The General Product Machine: a New Model for Symbolic FSM Traversal 548
Automatic Validation of Protocol Interfaces Described in VHDL 548
Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem 546
Diagnosis Oriented Test Pattern Generation 546
Testability measures with concurrent good simulation 544
Uso di Tecniche Evolutive per la Risoluzione di Problemi di CAD Elettronico 542
A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits 540
Evolutionary Techniques for Minimizing Test Signals Application Time 539
Early Power Estimation for System-on-Chip Designs 538
Using symbolic techniques to find the maximum clique in very large sparse graphs 538
Cross-fertilizing FSM Verification Techniques and Sequential Diagnosis 537
Simulation-based analysis of SEU effects on SRAM-based FPGAs 536
Exploiting symbolic techniques for partial scan flip flop selection 535
Partial scan flip flop selection for simulation-based sequential ATPGs 530
A portable ATPG tool for parallel and distributed systems 530
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits 528
Evolving Cellular Automata for Self-Testing Hardware 526
Integrating On-Line and Off-Line Testing of a Switching Memory in a Telecommunication System 523
Comparing ATPGs for synchronous sequential circuits 523
A test pattern generation methodology for low power consumption 522
A genetic algorithm for automatic generation of test logic for digital circuits 522
Finding the Maximurn Clique in a Graph Using BDDs 521
Integrating Online and Offline Testing of a Switching Memory 520
ARPIA: a High-Level Evolutionary Test Signal Generator 520
Circular self-test path for FSMs 520
Prediction of Power Requirements for High-Speed Circuits 518
Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets 517
A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs 515
Making the circular self-test path technique effective for real circuits 514
GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits 514
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms 513
Proving finite state machines correct with an automaton-based method 510
New Static Compaction Techniques of Test Sequences for Sequential Circuits 508
A new algorithm for diagnosis-oriented automatic test pattern generation 508
Self-checking and Fault Tolerant approaches can help BIST fault coverage: a case study 507
Fast sequential circuit test generation using high-level and gate-level techniques 507
Improving topological ATPG with symbolic techniques 506
Test Pattern Generation under Low Power Constraints 506
Role of fault injection techniques in system dependability analysis 506
Exact probabilistic testability measures for multi-output circuits 506
Speeding-up Fault Injection Campaigns in VHDL models 505
A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture 505
Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions 505
Optimizing area loss in flat glass cutting 504
Advanced Techniques for GA-based sequential ATPGs 504
A simulation-based approach to test pattern generation for synchronous circuits 502
Testability analysis and ATPG on behavioral RT-level VHDL 502
The Product Machine and Implicit Enumeration to prove FSMs correct 502
GA-Based Verification of Network Protocols Performance 501
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 500
Exploiting the background debugging mode in a fault injection system 500
Comparing topological, symbolic and GA-based ATPGs: an experimental approach 500
Testing a Switching Memory in a Telecommunication System 495
Random Testability Analysis: comparing and evaluating existing approaches 495
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms 491
Automatic Completion and Refinement of Verification Sets for Microprocessor Cores 488
Probabilistic Testability Analysis 487
Scan insertion criteria for low design impact 481
FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits 479
Boolean function manipulation on a parallel system using BDDs 478
Exploiting high-level descriptions for circuits fault tolerance assessment 477
Totale 57.353
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Categoria #
all - tutte 430.325
article - articoli 79.153
book - libri 3.032
conference - conferenze 329.798
curatela - curatele 777
other - altro 1.061
patent - brevetti 0
selected - selezionate 0
volume - volumi 16.504
Totale 860.650
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20208.048 0 0 0 0 0 1.667 1.215 1.829 1.715 733 502 387
2020/202110.311 1.339 1.614 456 1.359 554 971 547 765 629 1.008 704 365
2021/20226.817 447 564 189 244 314 444 292 405 256 783 1.141 1.738
2022/202312.174 950 1.729 823 816 1.047 1.441 1.675 517 1.168 118 619 1.271
2023/20243.880 288 386 257 283 411 417 233 271 105 148 379 702
2024/20258.787 608 2.492 842 2.523 1.286 1.036 0 0 0 0 0 0
Totale 171.791