PORTO @ Archivio Istituzionale della Ricerca

SONZA REORDA, MATTEO
 Distribuzione geografica
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Continente #
EU - Europa 94.469
NA - Nord America 69.213
AS - Asia 29.004
SA - Sud America 2.542
AF - Africa 436
OC - Oceania 48
Continente sconosciuto - Info sul continente non disponibili 34
Totale 195.746
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Nazione #
US - Stati Uniti d'America 68.135
IT - Italia 38.416
GB - Regno Unito 14.463
FR - Francia 12.433
DE - Germania 12.038
CN - Cina 10.575
SG - Singapore 10.472
RU - Federazione Russa 3.913
UA - Ucraina 3.646
BR - Brasile 2.056
NL - Olanda 2.005
TR - Turchia 1.820
KR - Corea 1.536
IE - Irlanda 1.218
SE - Svezia 1.139
CH - Svizzera 943
HK - Hong Kong 921
FI - Finlandia 743
IL - Israele 732
CA - Canada 687
JP - Giappone 568
AT - Austria 556
LT - Lituania 520
IN - India 517
PL - Polonia 517
BE - Belgio 458
VN - Vietnam 419
MX - Messico 327
PK - Pakistan 297
JO - Giordania 293
ID - Indonesia 207
BG - Bulgaria 168
RO - Romania 153
EE - Estonia 143
ES - Italia 138
AR - Argentina 128
EU - Europa 127
SN - Senegal 115
TW - Taiwan 114
IR - Iran 109
MY - Malesia 100
GR - Grecia 91
AP - ???statistics.table.value.countryCode.AP??? 85
CO - Colombia 85
BD - Bangladesh 84
IQ - Iraq 78
ZA - Sudafrica 75
DK - Danimarca 65
AE - Emirati Arabi Uniti 57
CL - Cile 57
CZ - Repubblica Ceca 57
EC - Ecuador 48
EG - Egitto 46
PT - Portogallo 45
MA - Marocco 44
AU - Australia 43
UZ - Uzbekistan 43
VE - Venezuela 43
TH - Thailandia 41
UY - Uruguay 41
SA - Arabia Saudita 39
BY - Bielorussia 35
BO - Bolivia 34
MD - Moldavia 33
PH - Filippine 28
DZ - Algeria 27
PE - Perù 26
GH - Ghana 24
AM - Armenia 23
NG - Nigeria 23
SK - Slovacchia (Repubblica Slovacca) 23
PY - Paraguay 22
TN - Tunisia 21
KZ - Kazakistan 19
NO - Norvegia 18
AL - Albania 17
CY - Cipro 17
CI - Costa d'Avorio 16
RS - Serbia 16
AZ - Azerbaigian 15
HR - Croazia 15
HU - Ungheria 14
LU - Lussemburgo 14
GT - Guatemala 13
SI - Slovenia 12
DO - Repubblica Dominicana 11
KE - Kenya 11
SC - Seychelles 11
KG - Kirghizistan 9
PA - Panama 9
JM - Giamaica 8
BA - Bosnia-Erzegovina 7
BH - Bahrain 7
LB - Libano 7
MK - Macedonia 7
QA - Qatar 7
GE - Georgia 6
LK - Sri Lanka 6
NP - Nepal 6
ET - Etiopia 5
Totale 195.654
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Città #
Torino 25.244
Ashburn 18.161
Southend 13.223
Seattle 7.335
Singapore 5.561
Fairfield 4.913
Turin 2.982
Chandler 2.748
Woodbridge 2.490
Houston 2.173
Boardman 2.104
Princeton 1.909
Cambridge 1.892
Zhengzhou 1.821
Jacksonville 1.743
Santa Clara 1.687
Wilmington 1.650
Ann Arbor 1.497
Beijing 1.401
Hangzhou 1.277
Saint Petersburg 1.214
Dublin 1.160
Berlin 1.159
Des Moines 1.060
Izmir 1.033
Milan 992
San Ramon 878
Bern 834
Shanghai 754
Chicago 718
Hefei 690
San Donato Milanese 652
Dallas 651
Hong Kong 642
Council Bluffs 608
Helsinki 586
Herkenbosch 546
Tongling 486
Zaporozhye 469
Bologna 454
Istanbul 450
Seoul 448
Baltimore 427
Mountain View 426
Pennsylvania Furnace 425
Overberg 393
Brussels 392
Tel Aviv 377
Monopoli 371
New York 367
Vienna 357
Buffalo 353
Kraków 317
Frankfurt am Main 313
Jerusalem 312
Amsterdam 287
San Diego 275
Los Angeles 272
Nuremberg 270
Padua 254
Waterloo 230
Frankfurt 214
Guangzhou 200
Malatya 194
Lecce 187
Fremont 186
San Francisco 182
São Paulo 181
Mexico City 180
Redwood City 178
Rome 177
Moscow 176
Rotterdam 169
London 164
Tokyo 160
Munich 158
North Bergen 158
Ho Chi Minh City 155
Shenzhen 155
Toronto 155
Jakarta 143
La Jolla 136
Dearborn 131
Melun 124
Bremen 123
Paris 122
Cedar Rapids 118
Hanoi 113
Kwai Chung 111
Ottawa 110
Norwalk 108
Tallinn 105
Atlanta 101
Las Vegas 96
Xi'an 92
Austin 90
Putian 88
Lappeenranta 87
Washington 85
Columbus 84
Totale 130.209
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Nome #
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms 1.555
On-line testing of an off-the-shelf microprocessor board for safety-critical applications 972
The use of model checking in ATPG for sequential circuits 921
EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards 853
On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors 829
A PVM tool for automatic test generation on parallel and distributed systems 812
FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems 809
A Functional Approach for Testing the Reorder Buffer Memory 800
La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti 793
A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits 791
Exploiting competing subpopulations for automatic generation of test sequences for digital circuits 761
An extended model to support detailed GPGPU reliability analysis 743
E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services 717
Simulation-Based Verification of Network Protocols Performance 694
TPDL*: Extended Temporal Profile Description Language 693
A Fault Injection Environment for Microprocessor-based Board 686
Il ruolo delle tecniche di fault injection nell’analisi dell’affidabilità dei sistemi 674
GATTO: A Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits 673
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits 669
A low cost programmable board for speeding-upfault-injection in Microprocessor based systems 651
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits 638
An Approach to Sequential Circuit Diagnosis Based on Formal Verification Techniques 616
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG 616
Cellular automata for deterministic sequential test pattern generation 612
Expressing logical and temporal conditions in simulation environments: TPDL* 612
C_TPDL* : adapting TPDL* to concurrent simulation environments 609
Fault Behavior Observation of a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment 609
A Hybrid Fault Injection Methodology for Real Time Systems 608
Fault Injection for Embedded Microprocessor-based Systems 606
A new model for improving symbolic Product Machine traversal 606
A diagnostic test pattern generation algorithm 605
Sequential circuit diagnosis based on formal verification techniques 604
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information 596
An integrated HW and SW fault injection environment for real-time systems 595
Automatic Validation of Protocol Interfaces Described in VHDL 592
Model Checking and Graph Theory in sequential ATPG 588
Initializability Analysis of Synchronous Sequential Circuits 588
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization 586
Guaranteeing testability in re-encoding for low power 586
An experimental comparison of different approaches to ROM BIST 583
Diagnosis Oriented Test Pattern Generation 583
The General Product Machine: a New Model for Symbolic FSM Traversal 582
Testability measures with concurrent good simulation 580
Cross-fertilizing FSM Verification Techniques and Sequential Diagnosis 574
Evolutionary Techniques for Minimizing Test Signals Application Time 572
Uso di Tecniche Evolutive per la Risoluzione di Problemi di CAD Elettronico 572
Early Power Estimation for System-on-Chip Designs 571
Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem 569
A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits 567
ARPIA: a High-Level Evolutionary Test Signal Generator 564
Simulation-based analysis of SEU effects on SRAM-based FPGAs 563
Exploiting symbolic techniques for partial scan flip flop selection 563
Advanced Techniques for GA-based sequential ATPGs 562
Using symbolic techniques to find the maximum clique in very large sparse graphs 561
Integrating On-Line and Off-Line Testing of a Switching Memory in a Telecommunication System 559
Evolving Cellular Automata for Self-Testing Hardware 559
Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets 556
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits 556
Prediction of Power Requirements for High-Speed Circuits 556
Partial scan flip flop selection for simulation-based sequential ATPGs 555
A portable ATPG tool for parallel and distributed systems 553
A test pattern generation methodology for low power consumption 552
Comparing ATPGs for synchronous sequential circuits 552
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms 552
Finding the Maximurn Clique in a Graph Using BDDs 551
Integrating Online and Offline Testing of a Switching Memory 549
A new algorithm for diagnosis-oriented automatic test pattern generation 549
Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors 546
A genetic algorithm for automatic generation of test logic for digital circuits 545
Proving finite state machines correct with an automaton-based method 543
Circular self-test path for FSMs 543
Speeding-up Fault Injection Campaigns in VHDL models 541
Improving topological ATPG with symbolic techniques 541
GA-Based Verification of Network Protocols Performance 540
Fast sequential circuit test generation using high-level and gate-level techniques 539
A simulation-based approach to test pattern generation for synchronous circuits 539
GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits 538
A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs 537
Test Pattern Generation under Low Power Constraints 537
Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions 536
Exact probabilistic testability measures for multi-output circuits 536
Making the circular self-test path technique effective for real circuits 535
New Static Compaction Techniques of Test Sequences for Sequential Circuits 534
RT-level ITC'99 benchmarks and first ATPG results 534
The Product Machine and Implicit Enumeration to prove FSMs correct 533
A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture 530
Random Testability Analysis: comparing and evaluating existing approaches 530
Optimizing area loss in flat glass cutting 529
Testability analysis and ATPG on behavioral RT-level VHDL 529
Comparing topological, symbolic and GA-based ATPGs: an experimental approach 528
Role of fault injection techniques in system dependability analysis 528
Self-checking and Fault Tolerant approaches can help BIST fault coverage: a case study 526
Testing a Switching Memory in a Telecommunication System 525
Functional Verification of DMA Controllers 524
Probabilistic Testability Analysis 523
FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits 518
Automatic Completion and Refinement of Verification Sets for Microprocessor Cores 516
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms 516
Exploiting the background debugging mode in a fault injection system 515
Boolean function manipulation on a parallel system using BDDs 514
Totale 60.881
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Categoria #
all - tutte 516.500
article - articoli 97.131
book - libri 3.701
conference - conferenze 394.209
curatela - curatele 910
other - altro 1.342
patent - brevetti 0
selected - selezionate 0
volume - volumi 19.207
Totale 1.033.000
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20214.980 0 0 0 0 0 968 547 763 629 1.006 703 364
2021/20226.803 447 563 189 242 313 443 291 405 256 783 1.135 1.736
2022/202312.126 949 1.725 823 814 1.047 1.436 1.672 516 1.155 116 613 1.260
2023/20243.850 284 386 255 280 406 414 231 271 102 147 377 697
2024/202520.992 605 2.479 842 2.510 1.282 1.368 970 2.254 2.874 910 1.767 3.131
2025/202613.054 1.983 2.282 2.590 3.116 2.842 241 0 0 0 0 0 0
Totale 196.667