Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.

A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits / Corno, Fulvio; Prinetto, Paolo Ernesto; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Squillero, Giovanni. - (1997), pp. 56-61. (Intervento presentato al convegno ATS '97, 6th Asian Test Symposium tenutosi a Akita (JPN) nel 17-19 Nov 1997) [10.1109/ATS.1997.643917].

A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits

CORNO, Fulvio;PRINETTO, Paolo Ernesto;REBAUDENGO, Maurizio;SONZA REORDA, Matteo;SQUILLERO, Giovanni
1997

Abstract

Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.
1997
0818682094
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1545099
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