Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%.

Speeding-up Fault Injection Campaigns in VHDL models / B., Parrotta; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo. - 1943:(2000), pp. 27-36. (Intervento presentato al convegno Computer Safety, Reliability and Security 19th International Conference, SAFECOMP 2000 tenutosi a Rotterdam (NLD) nel October 24–27, 2000) [10.1007/3-540-40891-6_3].

Speeding-up Fault Injection Campaigns in VHDL models

REBAUDENGO, Maurizio;SONZA REORDA, Matteo;VIOLANTE, MASSIMO
2000

Abstract

Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%.
2000
3540411860
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2374722
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