Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.

Early Power Estimation for System-on-Chip Designs / M., Lajolo; Lavagno, Luciano; SONZA REORDA, Matteo; Violante, Massimo. - 1918:(2000), pp. 108-117. (Intervento presentato al convegno Power and Timing Modeling, Optimization and Simulation 10th International Workshop, PATMOS 2000 tenutosi a Göttingen (DEU) nel Sep. 13-15, 2000) [10.1007/3-540-45373-3_11].

Early Power Estimation for System-on-Chip Designs

LAVAGNO, Luciano;SONZA REORDA, Matteo;VIOLANTE, MASSIMO
2000

Abstract

Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.
2000
3540410686
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2374680
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