In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small- or medium- sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC’99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies.
Automatic Validation of Protocol Interfaces Described in VHDL / Corno, Fulvio; SONZA REORDA, Matteo; Squillero, Giovanni. - 1803:(2000), pp. 205-213. (Intervento presentato al convegno EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoRob, and EvoFlight tenutosi a Edinburgh (GBR) nel April 17, 2000) [10.1007/3-540-45561-2_20].
Automatic Validation of Protocol Interfaces Described in VHDL
CORNO, Fulvio;SONZA REORDA, Matteo;SQUILLERO, Giovanni
2000
Abstract
In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small- or medium- sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC’99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies.Pubblicazioni consigliate
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https://hdl.handle.net/11583/1545254
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