Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its effectiveness is therefore a key factor. In this paper we propose to exploit FPGAs to speed-up Fault Injection for fault tolerance evaluation of VLSI circuits. A complete Fault Injection environment is described, relying on FPGA-based emulation of the circuit for fault effect analysis. The proposed approach allows combining the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided to support the feasibility and effectiveness of the approach. The work is partially funded by the Italian Ministry for University through the project “Sistemi di elaborazione reattivi ed affidabili per applicazioni industriali”, the Italian Space Agency through the basic research project “Definizione e valutazione di tecniche software per la realizzazione di sistemi di elaborazione tolleranti ai guasti a basso costo”, and by Politecnico di Torino through the Giovani Ricercatori project.

FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits / Civera, Pierluigi; Macchiarulo, Luca; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo. - 2147:(2001), pp. 493-502. ((Intervento presentato al convegno Field-Programmable Logic and Applications 11th International Conference, FPL 2001 tenutosi a Belfast (GBR) nel Aug. 27-29, 2001 [10.1007/3-540-44687-7_51].

FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits

CIVERA, PIERLUIGI;MACCHIARULO, Luca;REBAUDENGO, Maurizio;SONZA REORDA, Matteo;VIOLANTE, MASSIMO
2001

Abstract

Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its effectiveness is therefore a key factor. In this paper we propose to exploit FPGAs to speed-up Fault Injection for fault tolerance evaluation of VLSI circuits. A complete Fault Injection environment is described, relying on FPGA-based emulation of the circuit for fault effect analysis. The proposed approach allows combining the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided to support the feasibility and effectiveness of the approach. The work is partially funded by the Italian Ministry for University through the project “Sistemi di elaborazione reattivi ed affidabili per applicazioni industriali”, the Italian Space Agency through the basic research project “Definizione e valutazione di tecniche software per la realizzazione di sistemi di elaborazione tolleranti ai guasti a basso costo”, and by Politecnico di Torino through the Giovani Ricercatori project.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1498965
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