CALIMERA, ANDREA
 Distribuzione geografica
Continente #
EU - Europa 13.388
NA - Nord America 11.634
AS - Asia 1.792
AF - Africa 144
SA - Sud America 56
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 9
Totale 27.034
Nazione #
US - Stati Uniti d'America 11.518
IT - Italia 3.035
GB - Regno Unito 2.818
DE - Germania 2.730
FR - Francia 2.317
CN - Cina 1.014
UA - Ucraina 535
NL - Olanda 403
IE - Irlanda 377
RU - Federazione Russa 268
TR - Turchia 243
CH - Svizzera 200
FI - Finlandia 138
SE - Svezia 132
BE - Belgio 124
CA - Canada 111
SG - Singapore 108
SN - Senegal 105
IN - India 94
AT - Austria 77
KR - Corea 74
JO - Giordania 67
JP - Giappone 54
HK - Hong Kong 51
BG - Bulgaria 39
BR - Brasile 38
RO - Romania 33
EU - Europa 29
ES - Italia 23
GH - Ghana 19
IR - Iran 19
VN - Vietnam 18
TW - Taiwan 17
EE - Estonia 14
CZ - Repubblica Ceca 13
DK - Danimarca 11
MY - Malesia 11
CL - Cile 10
IL - Israele 10
AU - Australia 9
PK - Pakistan 9
PT - Portogallo 8
PE - Perù 6
PL - Polonia 6
EG - Egitto 5
KZ - Kazakistan 5
SA - Arabia Saudita 5
TH - Thailandia 5
ZA - Sudafrica 5
AP - ???statistics.table.value.countryCode.AP??? 4
BY - Bielorussia 4
GR - Grecia 4
NO - Norvegia 4
PH - Filippine 4
TN - Tunisia 4
AL - Albania 3
HR - Croazia 3
ID - Indonesia 3
LV - Lettonia 3
MX - Messico 3
QA - Qatar 3
UZ - Uzbekistan 3
AE - Emirati Arabi Uniti 2
AR - Argentina 2
BD - Bangladesh 2
IQ - Iraq 2
LU - Lussemburgo 2
MA - Marocco 2
NG - Nigeria 2
NZ - Nuova Zelanda 2
SI - Slovenia 2
BA - Bosnia-Erzegovina 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
KE - Kenya 1
LK - Sri Lanka 1
LT - Lituania 1
MO - Macao, regione amministrativa speciale della Cina 1
NP - Nepal 1
OM - Oman 1
PA - Panama 1
SY - Repubblica araba siriana 1
Totale 27.034
Città #
Ashburn 2.859
Southend 2.574
Seattle 1.456
Fairfield 929
Chandler 696
Turin 691
Torino 504
Woodbridge 484
Houston 432
Princeton 420
Ann Arbor 390
Dublin 362
Wilmington 357
Cambridge 332
Hangzhou 318
Boardman 287
Jacksonville 281
Berlin 250
Beijing 249
Izmir 193
Chicago 174
Bern 172
San Ramon 165
Frankfurt 158
Herkenbosch 144
Milan 140
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Helsinki 118
Rotterdam 107
Brussels 106
Shanghai 96
Zhengzhou 95
Des Moines 92
Zaporozhye 78
Mountain View 77
Vienna 76
Putian 75
Baltimore 70
Council Bluffs 68
Pennsylvania Furnace 66
Bologna 65
San Jose 61
Rome 59
Buffalo 57
Singapore 55
Monopoli 54
Redwood City 54
Lecce 52
San Francisco 48
Ottawa 47
Overberg 47
Dearborn 39
Fremont 36
Sofia 36
Guangzhou 34
San Diego 34
Malatya 31
Padua 30
Amsterdam 27
Moscow 27
Toronto 26
Falls Church 25
Norwalk 25
Seoul 25
Redmond 23
Porto Alegre 22
Washington 21
Andover 19
London 19
Overland Park 18
Paris 18
Bangalore 17
Columbus 17
Milano 17
Melun 16
Kansas City 15
Osaka 15
Chilliwack 14
Galati 14
New York 14
Rivoli 14
Barcelona 13
Frankfurt am Main 13
Miglianico 13
Jaipur 12
Venaria Reale 12
San Antonio 11
Cupertino 10
Dong Ket 10
Greenville 10
Imola 10
Las Vegas 10
Timisoara 10
Austin 9
Hefei 9
Hyderabad 9
Phoenix 9
San Mateo 9
Totale 17.976
Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 633
On-chip Thermal Modeling Based on SPICE Simulation 601
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 538
An on-chip all-digital PV-monitoring architecture for digital IPs 520
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 505
Modeling of thermally induced skew variations in clock distribution network 485
Aging Effects of Leakage Optimizations for Caches 426
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 423
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 384
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 368
Buffering of frequent accesses for reduced cache aging 363
Partitioned cache architectures for reduced NBTI-induced aging 362
The Human Brain Project and Neuromorphic computing 350
Power-Gating: More Than Leakage Savings 346
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 345
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 331
An integrated thermal estimation framework for industrial embedded platforms. 319
An integrated thermal estimation framework for industrial embedded platforms 318
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 314
Design Techniques and Architectures for Low-Leakage SRAMs 312
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 304
Characterizing the activity factor in NBTI aging models for embedded cores 298
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 298
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 297
Delay model for reconfigurable logic gates based on graphene PN-junctions 297
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 293
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 291
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 290
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 290
Exploration of different implementation styles for graphene-based reconfigurable gates 286
Dual-Vt Assignment Policies in ITD-Aware Synthesis 285
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 283
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 283
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 280
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 269
Energy-optimal caches with guaranteed lifetime 267
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 266
NBTI effects on tree-like clock distribution networks 264
Modeling of Physical Defects in PN-Junction Based Graphene Devices 262
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 262
Power Modeling and Characterization of Graphene-Based Logic Gates 260
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 259
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 259
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 255
NBTI-Aware Clustered Power Gating 254
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 253
IR-Drop Analysis of Graphene-Based Power Distribution Networks 251
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 248
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 244
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 241
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 239
Design Techniques for NBTI-Tolerant Power-Gating Architectures 236
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 234
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 231
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 231
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 231
Placement-aware clustering for integrated clock and power gating 229
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 228
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 222
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 221
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 221
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 220
Enabling concurrent clock and power gating in an industrial design flow 219
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 218
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 217
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 217
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 213
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 212
Post-placement temperature reduction techniques 212
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 209
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 208
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 198
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 198
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 197
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 183
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 178
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 162
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 160
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 159
Activation-kernel extraction through machine learning 159
Power and Aging Characterization of Digital FIR Filters Architectures 157
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 156
All-digital embedded meters for on-line power estimation 151
ACME: An energy-efficient approximate bus encoding for I2C 151
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 145
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores 111
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 109
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 104
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits 103
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 103
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 100
Enabling monocular depth perception at the very edge 99
Ultra-compact binary neural networks for human activity recognition on RISC-V processors 98
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 97
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling 96
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling 96
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator 94
Multiplication by Inference using Classification Trees: A Case-Study Analysis 89
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis 89
Monocular Depth Perception on Microcontrollers for Edge Applications 89
Totale 24.931
Categoria #
all - tutte 63.530
article - articoli 16.273
book - libri 0
conference - conferenze 45.388
curatela - curatele 211
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 1.658
Totale 127.060


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20191.080 0 0 0 0 0 0 0 0 0 0 568 512
2019/20203.398 269 232 160 450 482 324 288 428 377 194 123 71
2020/20212.329 245 341 67 309 164 188 122 196 153 208 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/2024865 43 87 149 84 102 110 39 48 16 86 101 0
Totale 27.372