PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
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Continente #
EU - Europa 13.513
NA - Nord America 12.135
AS - Asia 2.266
AF - Africa 144
SA - Sud America 59
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 9
Totale 28.137
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Nazione #
US - Stati Uniti d'America 12.019
IT - Italia 3.114
GB - Regno Unito 2.818
DE - Germania 2.735
FR - Francia 2.321
CN - Cina 1.147
UA - Ucraina 535
SG - Singapore 408
NL - Olanda 407
IE - Irlanda 378
RU - Federazione Russa 274
TR - Turchia 243
CH - Svizzera 200
FI - Finlandia 144
BE - Belgio 137
SE - Svezia 133
CA - Canada 111
SN - Senegal 105
IN - India 103
KR - Corea 94
AT - Austria 79
JO - Giordania 67
HK - Hong Kong 56
JP - Giappone 55
BG - Bulgaria 40
BR - Brasile 40
RO - Romania 33
EU - Europa 29
ES - Italia 23
TW - Taiwan 22
GH - Ghana 19
IR - Iran 19
VN - Vietnam 18
CZ - Repubblica Ceca 15
EE - Estonia 15
DK - Danimarca 11
MY - Malesia 11
CL - Cile 10
IL - Israele 10
AU - Australia 9
PK - Pakistan 9
PT - Portogallo 8
PE - Perù 6
PL - Polonia 6
EG - Egitto 5
KZ - Kazakistan 5
SA - Arabia Saudita 5
TH - Thailandia 5
ZA - Sudafrica 5
AP - ???statistics.table.value.countryCode.AP??? 4
BY - Bielorussia 4
GR - Grecia 4
NO - Norvegia 4
PH - Filippine 4
TN - Tunisia 4
AL - Albania 3
HR - Croazia 3
ID - Indonesia 3
LV - Lettonia 3
MX - Messico 3
QA - Qatar 3
UZ - Uzbekistan 3
AE - Emirati Arabi Uniti 2
AR - Argentina 2
BD - Bangladesh 2
IQ - Iraq 2
LU - Lussemburgo 2
MA - Marocco 2
NG - Nigeria 2
NZ - Nuova Zelanda 2
SI - Slovenia 2
AM - Armenia 1
BA - Bosnia-Erzegovina 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
KE - Kenya 1
LK - Sri Lanka 1
LT - Lituania 1
MO - Macao, regione amministrativa speciale della Cina 1
NP - Nepal 1
OM - Oman 1
PA - Panama 1
SY - Repubblica araba siriana 1
UY - Uruguay 1
Totale 28.137
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Città #
Ashburn 2.861
Southend 2.574
Seattle 1.456
Fairfield 929
Turin 733
Chandler 696
Torino 504
Woodbridge 484
Boardman 464
Houston 432
Princeton 420
Ann Arbor 390
Dublin 363
Wilmington 357
Cambridge 332
Hangzhou 318
Singapore 298
Jacksonville 281
Berlin 250
Beijing 249
Izmir 193
Chicago 174
Bern 172
San Ramon 165
Frankfurt 158
Milan 147
Herkenbosch 144
Bremen 126
San Donato Milanese 122
Helsinki 121
Saint Petersburg 121
Brussels 118
Rotterdam 109
Shanghai 99
Zhengzhou 95
Des Moines 92
Vienna 78
Zaporozhye 78
Mountain View 77
Putian 75
Baltimore 70
Council Bluffs 68
Pennsylvania Furnace 66
Bologna 65
Rome 62
San Jose 61
Buffalo 57
Monopoli 54
Redwood City 54
Lecce 52
San Francisco 51
Santa Clara 51
Ottawa 47
Overberg 47
Dearborn 39
Las Vegas 39
Fremont 36
Sofia 36
Guangzhou 34
San Diego 34
Moscow 32
Malatya 31
Padua 30
Amsterdam 29
Toronto 26
Falls Church 25
Norwalk 25
Seoul 25
New York 24
Redmond 23
Porto Alegre 22
Washington 21
Andover 19
Jaipur 19
London 19
Overland Park 18
Paris 18
Bangalore 17
Columbus 17
Milano 17
Melun 16
Kansas City 15
Osaka 15
Staten Island 15
Chilliwack 14
Galati 14
Miami 14
Rivoli 14
Barcelona 13
Frankfurt am Main 13
Miglianico 13
Venaria Reale 12
San Antonio 11
Cupertino 10
Dong Ket 10
Greenville 10
Hefei 10
Imola 10
Lappeenranta 10
Timisoara 10
Totale 18.584
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Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 641
On-chip Thermal Modeling Based on SPICE Simulation 610
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 547
An on-chip all-digital PV-monitoring architecture for digital IPs 530
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 512
Modeling of thermally induced skew variations in clock distribution network 499
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 434
Aging Effects of Leakage Optimizations for Caches 433
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 390
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 376
Buffering of frequent accesses for reduced cache aging 371
Partitioned cache architectures for reduced NBTI-induced aging 368
Power-Gating: More Than Leakage Savings 360
The Human Brain Project and Neuromorphic computing 359
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 350
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 335
An integrated thermal estimation framework for industrial embedded platforms. 327
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 326
An integrated thermal estimation framework for industrial embedded platforms 324
Design Techniques and Architectures for Low-Leakage SRAMs 318
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 310
Characterizing the activity factor in NBTI aging models for embedded cores 307
Delay model for reconfigurable logic gates based on graphene PN-junctions 306
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 304
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 301
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 297
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 296
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 295
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 294
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 292
Exploration of different implementation styles for graphene-based reconfigurable gates 290
Dual-Vt Assignment Policies in ITD-Aware Synthesis 289
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 287
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 285
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 276
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 275
NBTI effects on tree-like clock distribution networks 272
Energy-optimal caches with guaranteed lifetime 270
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 267
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 267
Modeling of Physical Defects in PN-Junction Based Graphene Devices 265
Power Modeling and Characterization of Graphene-Based Logic Gates 264
IR-Drop Analysis of Graphene-Based Power Distribution Networks 263
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 263
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 261
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 259
NBTI-Aware Clustered Power Gating 258
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 256
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 253
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 251
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 248
Design Techniques for NBTI-Tolerant Power-Gating Architectures 240
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 238
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 237
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 237
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 235
Placement-aware clustering for integrated clock and power gating 233
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 231
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 227
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 225
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 225
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 225
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 223
Enabling concurrent clock and power gating in an industrial design flow 223
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 222
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 222
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 221
Post-placement temperature reduction techniques 218
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 217
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 215
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 215
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 205
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 201
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 200
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 189
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 183
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 167
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 166
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 165
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 164
Activation-kernel extraction through machine learning 163
Power and Aging Characterization of Digital FIR Filters Architectures 162
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 162
All-digital embedded meters for on-line power estimation 157
ACME: An energy-efficient approximate bus encoding for I2C 154
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 123
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores 118
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 117
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits 115
Enabling monocular depth perception at the very edge 112
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 112
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator 110
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 110
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 106
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling 106
Ultra-compact binary neural networks for human activity recognition on RISC-V processors 105
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling 102
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 101
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis 99
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets 99
Totale 25.633
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Categoria #
all - tutte 69.526
article - articoli 18.068
book - libri 0
conference - conferenze 49.274
curatela - curatele 247
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 1.937
Totale 139.052
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.737 0 0 0 450 482 324 288 428 377 194 123 71
2020/20212.329 245 341 67 309 164 188 122 196 153 208 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/2025892 53 552 258 29 0 0 0 0 0 0 0 0
Totale 28.481