PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
EU - Europa 13.798
NA - Nord America 12.759
AS - Asia 2.868
AF - Africa 157
SA - Sud America 157
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 9
Totale 29.759
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 12.630
IT - Italia 3.177
GB - Regno Unito 2.836
DE - Germania 2.753
FR - Francia 2.325
CN - Cina 1.261
SG - Singapore 628
UA - Ucraina 536
NL - Olanda 412
RU - Federazione Russa 409
IE - Irlanda 382
TR - Turchia 372
CH - Svizzera 202
FI - Finlandia 151
BE - Belgio 147
KR - Corea 144
BR - Brasile 135
SE - Svezia 133
CA - Canada 123
SN - Senegal 105
IN - India 104
AT - Austria 88
JO - Giordania 68
HK - Hong Kong 61
ID - Indonesia 60
JP - Giappone 57
BG - Bulgaria 40
RO - Romania 33
EU - Europa 29
TW - Taiwan 24
ES - Italia 23
GH - Ghana 19
IR - Iran 19
VN - Vietnam 18
CZ - Repubblica Ceca 16
EE - Estonia 16
IL - Israele 14
MA - Marocco 13
DK - Danimarca 11
MY - Malesia 11
PK - Pakistan 11
CL - Cile 10
AU - Australia 9
PT - Portogallo 8
PL - Polonia 7
LT - Lituania 6
PE - Perù 6
AE - Emirati Arabi Uniti 5
EG - Egitto 5
KZ - Kazakistan 5
SA - Arabia Saudita 5
TH - Thailandia 5
ZA - Sudafrica 5
AL - Albania 4
AP - ???statistics.table.value.countryCode.AP??? 4
BD - Bangladesh 4
BY - Bielorussia 4
GR - Grecia 4
IQ - Iraq 4
NO - Norvegia 4
PH - Filippine 4
TN - Tunisia 4
UZ - Uzbekistan 4
AM - Armenia 3
AR - Argentina 3
HR - Croazia 3
LV - Lettonia 3
MX - Messico 3
QA - Qatar 3
KE - Kenya 2
LK - Sri Lanka 2
LU - Lussemburgo 2
NG - Nigeria 2
NZ - Nuova Zelanda 2
SI - Slovenia 2
AZ - Azerbaigian 1
BA - Bosnia-Erzegovina 1
CI - Costa d'Avorio 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
EC - Ecuador 1
GY - Guiana 1
KG - Kirghizistan 1
KW - Kuwait 1
LB - Libano 1
MO - Macao, regione amministrativa speciale della Cina 1
NP - Nepal 1
OM - Oman 1
PA - Panama 1
PR - Porto Rico 1
SY - Repubblica araba siriana 1
UY - Uruguay 1
Totale 29.759
Salva come PNG Salva come JPEG
Città #
Ashburn 2.865
Southend 2.574
Seattle 1.456
Fairfield 929
Turin 770
Chandler 696
Torino 504
Woodbridge 484
Singapore 483
Boardman 464
Houston 432
Princeton 420
Ann Arbor 390
Dublin 365
Wilmington 357
Cambridge 332
Hangzhou 318
Santa Clara 318
Jacksonville 281
Beijing 251
Berlin 250
Izmir 193
Chicago 174
Bern 172
San Ramon 165
Frankfurt 158
Milan 155
Herkenbosch 144
Brussels 128
Helsinki 128
Istanbul 127
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Rotterdam 109
Shanghai 100
Zhengzhou 95
Des Moines 92
Vienna 83
Council Bluffs 80
Zaporozhye 78
Mountain View 77
Putian 75
Baltimore 70
Pennsylvania Furnace 66
Bologna 65
Rome 64
San Jose 61
Jakarta 58
Buffalo 57
Monopoli 54
Redwood City 54
Ottawa 53
Lecce 52
San Francisco 51
Overberg 47
Dearborn 39
Las Vegas 39
Fremont 36
Guangzhou 36
Sofia 36
Moscow 34
San Diego 34
Amsterdam 32
Toronto 32
Malatya 31
Padua 30
Falls Church 25
Norwalk 25
Seoul 25
New York 24
Porto Alegre 23
Redmond 23
London 22
Frankfurt am Main 21
Washington 21
Yubileyny 20
Andover 19
Jaipur 19
Overland Park 18
Paris 18
Bangalore 17
Columbus 17
Milano 17
Nuremberg 17
Melun 16
Kansas City 15
Osaka 15
Staten Island 15
São Paulo 15
Chilliwack 14
Galati 14
Miami 14
Rivoli 14
Barcelona 13
Miglianico 13
Venaria Reale 12
Hong Kong 11
San Antonio 11
Shenzhen 11
Totale 19.346
Salva come PNG Salva come JPEG
Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 650
On-chip Thermal Modeling Based on SPICE Simulation 621
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 556
An on-chip all-digital PV-monitoring architecture for digital IPs 537
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 523
Modeling of thermally induced skew variations in clock distribution network 512
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 446
Aging Effects of Leakage Optimizations for Caches 442
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 398
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 384
Buffering of frequent accesses for reduced cache aging 383
Partitioned cache architectures for reduced NBTI-induced aging 378
Power-Gating: More Than Leakage Savings 373
The Human Brain Project and Neuromorphic computing 366
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 362
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 345
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 336
An integrated thermal estimation framework for industrial embedded platforms. 333
An integrated thermal estimation framework for industrial embedded platforms 331
Design Techniques and Architectures for Low-Leakage SRAMs 325
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 324
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 322
Characterizing the activity factor in NBTI aging models for embedded cores 319
Delay model for reconfigurable logic gates based on graphene PN-junctions 317
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 313
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 306
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 305
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 305
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 304
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 301
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 301
Exploration of different implementation styles for graphene-based reconfigurable gates 299
Dual-Vt Assignment Policies in ITD-Aware Synthesis 295
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 293
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 288
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 284
NBTI effects on tree-like clock distribution networks 282
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 279
Energy-optimal caches with guaranteed lifetime 278
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 276
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 275
IR-Drop Analysis of Graphene-Based Power Distribution Networks 274
Modeling of Physical Defects in PN-Junction Based Graphene Devices 274
Power Modeling and Characterization of Graphene-Based Logic Gates 274
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 269
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 268
NBTI-Aware Clustered Power Gating 264
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 264
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 263
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 258
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 258
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 246
Design Techniques for NBTI-Tolerant Power-Gating Architectures 244
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 244
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 242
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 241
Placement-aware clustering for integrated clock and power gating 240
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 236
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 236
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 233
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 233
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 232
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 231
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 231
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 230
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 230
Enabling concurrent clock and power gating in an industrial design flow 230
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 229
Post-placement temperature reduction techniques 228
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 225
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 223
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 216
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 207
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 206
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 196
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 196
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 184
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 183
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 177
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 172
Activation-kernel extraction through machine learning 171
ACME: An energy-efficient approximate bus encoding for I2C 171
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 170
Power and Aging Characterization of Digital FIR Filters Architectures 168
All-digital embedded meters for on-line power estimation 167
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 137
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores 137
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 134
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 133
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 131
Enabling monocular depth perception at the very edge 124
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 124
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits 122
Ultra-compact binary neural networks for human activity recognition on RISC-V processors 122
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator 121
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 119
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling 116
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling 114
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 113
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 112
Totale 26.660
Salva come PNG Salva come JPEG
Categoria #
all - tutte 76.652
article - articoli 20.139
book - libri 0
conference - conferenze 53.974
curatela - curatele 288
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.251
Totale 153.304
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.193 0 0 0 0 0 0 0 428 377 194 123 71
2020/20212.329 245 341 67 309 164 188 122 196 153 208 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20252.520 53 552 258 780 271 179 297 130 0 0 0 0
Totale 30.109