PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
EU - Europa 13.998
NA - Nord America 12.898
AS - Asia 3.692
SA - Sud America 324
AF - Africa 168
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 10
Totale 31.101
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 12.762
IT - Italia 3.196
GB - Regno Unito 2.836
DE - Germania 2.824
FR - Francia 2.325
SG - Singapore 1.318
CN - Cina 1.293
UA - Ucraina 538
RU - Federazione Russa 416
NL - Olanda 412
IE - Irlanda 382
TR - Turchia 375
BR - Brasile 290
CH - Svizzera 203
AT - Austria 180
KR - Corea 169
FI - Finlandia 151
BE - Belgio 147
SE - Svezia 133
CA - Canada 123
SN - Senegal 107
IN - India 105
HK - Hong Kong 92
JO - Giordania 69
ID - Indonesia 60
JP - Giappone 57
VN - Vietnam 43
BG - Bulgaria 41
RO - Romania 34
EU - Europa 29
ES - Italia 27
TW - Taiwan 26
GH - Ghana 19
IR - Iran 19
CZ - Repubblica Ceca 17
IL - Israele 17
EE - Estonia 16
MA - Marocco 14
PK - Pakistan 13
DK - Danimarca 11
MY - Malesia 11
CL - Cile 10
AU - Australia 9
IQ - Iraq 9
MX - Messico 8
PT - Portogallo 8
ZA - Sudafrica 8
EG - Egitto 7
PL - Polonia 7
AR - Argentina 6
LT - Lituania 6
PE - Perù 6
AE - Emirati Arabi Uniti 5
GR - Grecia 5
KZ - Kazakistan 5
SA - Arabia Saudita 5
TH - Thailandia 5
TN - Tunisia 5
UZ - Uzbekistan 5
AL - Albania 4
AP - ???statistics.table.value.countryCode.AP??? 4
BD - Bangladesh 4
BY - Bielorussia 4
EC - Ecuador 4
NO - Norvegia 4
PH - Filippine 4
AM - Armenia 3
AZ - Azerbaigian 3
HR - Croazia 3
LV - Lettonia 3
QA - Qatar 3
UY - Uruguay 3
CI - Costa d'Avorio 2
DO - Repubblica Dominicana 2
KE - Kenya 2
LB - Libano 2
LK - Sri Lanka 2
LU - Lussemburgo 2
NG - Nigeria 2
NZ - Nuova Zelanda 2
SI - Slovenia 2
AO - Angola 1
BA - Bosnia-Erzegovina 1
BO - Bolivia 1
CO - Colombia 1
DZ - Algeria 1
GY - Guiana 1
JM - Giamaica 1
KG - Kirghizistan 1
KW - Kuwait 1
MO - Macao, regione amministrativa speciale della Cina 1
NP - Nepal 1
OM - Oman 1
PA - Panama 1
PR - Porto Rico 1
PY - Paraguay 1
SY - Repubblica araba siriana 1
VE - Venezuela 1
XK - ???statistics.table.value.countryCode.XK??? 1
Totale 31.101
Salva come PNG Salva come JPEG
Città #
Ashburn 2.868
Southend 2.574
Seattle 1.456
Fairfield 929
Turin 786
Chandler 696
Singapore 510
Torino 504
Woodbridge 484
Boardman 467
Houston 432
Princeton 420
Ann Arbor 390
Dublin 365
Wilmington 357
Cambridge 332
Hangzhou 318
Santa Clara 318
Jacksonville 281
Beijing 251
Berlin 250
Izmir 193
Chicago 174
Bern 172
San Ramon 165
Frankfurt 158
Milan 158
Herkenbosch 144
Brussels 128
Helsinki 128
Istanbul 128
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Vienna 120
Rotterdam 109
Shanghai 100
Zhengzhou 96
Des Moines 92
Council Bluffs 86
Nuremberg 85
Zaporozhye 78
Mountain View 77
Putian 75
Baltimore 70
Pennsylvania Furnace 66
Bologna 65
Rome 64
San Jose 61
Jakarta 58
Buffalo 57
Monopoli 54
Redwood City 54
Ottawa 53
Lecce 52
San Francisco 51
Overberg 47
Hong Kong 41
Dearborn 39
Las Vegas 39
Moscow 37
Sofia 37
Fremont 36
Guangzhou 36
San Diego 34
Amsterdam 32
Toronto 32
Malatya 31
Padua 30
São Paulo 29
Falls Church 25
Norwalk 25
Porto Alegre 25
Seoul 25
New York 24
Redmond 23
London 22
Frankfurt am Main 21
Washington 21
Yubileyny 20
Andover 19
Jaipur 19
Overland Park 18
Paris 18
Bangalore 17
Columbus 17
Milano 17
Melun 16
Kansas City 15
Osaka 15
Staten Island 15
Chilliwack 14
Galati 14
Ho Chi Minh City 14
Miami 14
Rivoli 14
Barcelona 13
Hanoi 13
Miglianico 13
Venaria Reale 12
Totale 19.566
Salva come PNG Salva come JPEG
Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 659
On-chip Thermal Modeling Based on SPICE Simulation 634
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 568
An on-chip all-digital PV-monitoring architecture for digital IPs 548
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 535
Modeling of thermally induced skew variations in clock distribution network 527
Aging Effects of Leakage Optimizations for Caches 458
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 451
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 411
Buffering of frequent accesses for reduced cache aging 397
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 393
Partitioned cache architectures for reduced NBTI-induced aging 391
Power-Gating: More Than Leakage Savings 382
The Human Brain Project and Neuromorphic computing 373
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 368
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 364
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 343
An integrated thermal estimation framework for industrial embedded platforms. 341
An integrated thermal estimation framework for industrial embedded platforms 338
Design Techniques and Architectures for Low-Leakage SRAMs 334
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 332
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 332
Characterizing the activity factor in NBTI aging models for embedded cores 328
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 326
Delay model for reconfigurable logic gates based on graphene PN-junctions 323
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 314
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 313
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 312
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 312
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 311
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 307
Exploration of different implementation styles for graphene-based reconfigurable gates 305
Dual-Vt Assignment Policies in ITD-Aware Synthesis 302
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 302
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 300
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 296
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 292
NBTI effects on tree-like clock distribution networks 288
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 285
Energy-optimal caches with guaranteed lifetime 284
Modeling of Physical Defects in PN-Junction Based Graphene Devices 281
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 280
IR-Drop Analysis of Graphene-Based Power Distribution Networks 279
Power Modeling and Characterization of Graphene-Based Logic Gates 279
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 277
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 276
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 272
NBTI-Aware Clustered Power Gating 271
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 270
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 270
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 262
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 252
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 252
Design Techniques for NBTI-Tolerant Power-Gating Architectures 251
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 249
Placement-aware clustering for integrated clock and power gating 249
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 247
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 244
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 244
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 241
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 241
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 241
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 240
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 239
Enabling concurrent clock and power gating in an industrial design flow 239
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 237
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 236
Post-placement temperature reduction techniques 235
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 235
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 230
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 229
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 224
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 215
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 214
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 205
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 202
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 197
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 194
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 186
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 179
ACME: An energy-efficient approximate bus encoding for I2C 179
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 178
Activation-kernel extraction through machine learning 177
Power and Aging Characterization of Digital FIR Filters Architectures 175
All-digital embedded meters for on-line power estimation 169
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 160
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 153
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores 145
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 142
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 140
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 139
Enabling monocular depth perception at the very edge 134
Ultra-compact binary neural networks for human activity recognition on RISC-V processors 133
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator 131
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 130
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits 128
On the Efficiency of Early Bird Sampling (EBS) an Error Detection-Correction Scheme for Data-Driven Voltage Over-Scaling 127
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 126
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 122
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling 121
Totale 27.552
Salva come PNG Salva come JPEG
Categoria #
all - tutte 80.419
article - articoli 21.235
book - libri 0
conference - conferenze 56.468
curatela - curatele 308
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.408
Totale 160.838
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020388 0 0 0 0 0 0 0 0 0 194 123 71
2020/20212.329 245 341 67 309 164 188 122 196 153 208 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20253.864 53 552 258 780 271 179 297 456 775 243 0 0
Totale 31.453