PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
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Continente #
EU - Europa 14.384
NA - Nord America 13.846
AS - Asia 6.648
SA - Sud America 653
AF - Africa 201
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 11
Totale 35.758
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Nazione #
US - Stati Uniti d'America 13.668
IT - Italia 3.290
DE - Germania 2.893
GB - Regno Unito 2.866
SG - Singapore 2.709
FR - Francia 2.411
CN - Cina 2.331
BR - Brasile 550
UA - Ucraina 542
RU - Federazione Russa 424
NL - Olanda 417
TR - Turchia 387
IE - Irlanda 382
KR - Corea 259
CH - Svizzera 204
AT - Austria 196
HK - Hong Kong 196
VN - Vietnam 195
FI - Finlandia 176
BE - Belgio 147
SE - Svezia 142
IN - India 141
CA - Canada 136
SN - Senegal 108
JO - Giordania 79
JP - Giappone 76
ID - Indonesia 70
BG - Bulgaria 42
ES - Italia 41
RO - Romania 35
AR - Argentina 34
IQ - Iraq 34
EU - Europa 29
TW - Taiwan 26
MX - Messico 25
BD - Bangladesh 21
ZA - Sudafrica 21
IR - Iran 20
MA - Marocco 20
GH - Ghana 19
PL - Polonia 19
IL - Israele 18
CZ - Repubblica Ceca 17
PK - Pakistan 17
EE - Estonia 16
CL - Cile 15
AU - Australia 13
MY - Malesia 13
VE - Venezuela 13
EC - Ecuador 12
DK - Danimarca 11
SA - Arabia Saudita 11
AE - Emirati Arabi Uniti 10
CO - Colombia 10
EG - Egitto 10
PT - Portogallo 10
UZ - Uzbekistan 10
AL - Albania 9
KZ - Kazakistan 8
PE - Perù 8
LT - Lituania 7
BY - Bielorussia 6
PH - Filippine 6
TN - Tunisia 6
AZ - Azerbaigian 5
GR - Grecia 5
LB - Libano 5
OM - Oman 5
TH - Thailandia 5
AP - ???statistics.table.value.countryCode.AP??? 4
DZ - Algeria 4
KE - Kenya 4
NO - Norvegia 4
SY - Repubblica araba siriana 4
UY - Uruguay 4
AM - Armenia 3
CY - Cipro 3
HR - Croazia 3
LV - Lettonia 3
NP - Nepal 3
PY - Paraguay 3
QA - Qatar 3
BB - Barbados 2
BO - Bolivia 2
CI - Costa d'Avorio 2
DO - Repubblica Dominicana 2
GY - Guiana 2
HN - Honduras 2
JM - Giamaica 2
KG - Kirghizistan 2
KW - Kuwait 2
LK - Sri Lanka 2
LU - Lussemburgo 2
NG - Nigeria 2
NZ - Nuova Zelanda 2
PA - Panama 2
PR - Porto Rico 2
PS - Palestinian Territory 2
SI - Slovenia 2
XK - ???statistics.table.value.countryCode.XK??? 2
Totale 35.743
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Città #
Ashburn 3.136
Southend 2.574
Seattle 1.456
Singapore 1.370
Fairfield 929
Turin 829
Chandler 696
Torino 504
Woodbridge 484
Beijing 483
Boardman 467
Houston 434
Princeton 420
Ann Arbor 391
Dublin 365
Wilmington 357
Santa Clara 338
Cambridge 332
Hangzhou 320
Jacksonville 281
Berlin 250
Dallas 213
Izmir 194
Chicago 177
Bern 172
Milan 171
San Ramon 165
Frankfurt 158
Herkenbosch 144
Tongling 143
Hong Kong 141
Istanbul 131
Helsinki 130
Brussels 128
Bremen 126
Vienna 125
San Donato Milanese 122
Saint Petersburg 121
Rotterdam 109
Shanghai 109
Council Bluffs 100
Zhengzhou 100
Buffalo 98
Des Moines 92
Nuremberg 91
Hefei 82
Zaporozhye 78
Mountain View 77
San Jose 76
Putian 75
Seoul 75
Baltimore 70
Ho Chi Minh City 68
Pennsylvania Furnace 66
Rome 66
Bologna 65
Jakarta 58
San Francisco 57
Monopoli 55
Ottawa 54
Redwood City 54
Los Angeles 53
Lecce 52
Hanoi 51
São Paulo 49
Guangzhou 47
Overberg 47
Frankfurt am Main 42
Las Vegas 41
New York 41
Munich 40
Dearborn 39
Moscow 38
Sofia 37
Amsterdam 36
Fremont 36
San Diego 34
Toronto 34
Malatya 31
North Bergen 30
Padua 30
Porto Alegre 30
London 29
Tokyo 28
Columbus 27
The Dalles 27
Falls Church 25
Lauterbourg 25
Norwalk 25
Redmond 23
Washington 22
Lappeenranta 21
Phoenix 21
Redondo Beach 21
Jaipur 20
Paris 20
Yubileyny 20
Andover 19
Overland Park 18
Bangalore 17
Totale 21.998
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Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 691
On-chip Thermal Modeling Based on SPICE Simulation 660
Modeling of thermally induced skew variations in clock distribution network 597
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 591
An on-chip all-digital PV-monitoring architecture for digital IPs 574
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 557
Aging Effects of Leakage Optimizations for Caches 500
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 500
Buffering of frequent accesses for reduced cache aging 446
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 438
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 433
Partitioned cache architectures for reduced NBTI-induced aging 431
Power-Gating: More Than Leakage Savings 420
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 405
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 392
The Human Brain Project and Neuromorphic computing 386
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 370
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 367
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 362
An integrated thermal estimation framework for industrial embedded platforms 362
Design Techniques and Architectures for Low-Leakage SRAMs 359
An integrated thermal estimation framework for industrial embedded platforms. 358
Delay model for reconfigurable logic gates based on graphene PN-junctions 351
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 349
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 346
Characterizing the activity factor in NBTI aging models for embedded cores 344
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 338
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 338
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 336
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 334
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 333
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 332
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 331
Exploration of different implementation styles for graphene-based reconfigurable gates 329
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 328
Dual-Vt Assignment Policies in ITD-Aware Synthesis 324
NBTI effects on tree-like clock distribution networks 323
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 319
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 316
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 307
Modeling of Physical Defects in PN-Junction Based Graphene Devices 306
Energy-optimal caches with guaranteed lifetime 306
IR-Drop Analysis of Graphene-Based Power Distribution Networks 305
Power Modeling and Characterization of Graphene-Based Logic Gates 304
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 301
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 297
NBTI-Aware Clustered Power Gating 294
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 292
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 291
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 291
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 289
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 282
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 276
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 274
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 272
Placement-aware clustering for integrated clock and power gating 270
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 270
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 269
Design Techniques for NBTI-Tolerant Power-Gating Architectures 268
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 266
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 266
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 266
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 265
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 265
Enabling concurrent clock and power gating in an industrial design flow 263
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 263
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 261
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 258
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 257
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 255
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 254
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 254
Post-placement temperature reduction techniques 253
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 250
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 246
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 238
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 237
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 235
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 217
ACME: An energy-efficient approximate bus encoding for I2C 214
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 211
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 207
Activation-kernel extraction through machine learning 206
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 197
All-digital embedded meters for on-line power estimation 195
Power and Aging Characterization of Digital FIR Filters Architectures 191
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 187
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 180
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference 178
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 177
Enabling monocular depth perception at the very edge 176
Optimality Assessment of Memory-Bounded ConvNets Deployed on Resource-Constrained RISC Cores 175
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 174
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 171
Monocular Depth Perception on Microcontrollers for Edge Applications 165
Ultra-compact binary neural networks for human activity recognition on RISC-V processors 164
Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption 158
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator 155
Efficacy of topology scaling for temperature and latency constrained embedded convnets 155
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 155
Totale 30.494
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Categoria #
all - tutte 95.477
article - articoli 25.555
book - libri 0
conference - conferenze 66.519
curatela - curatele 386
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.017
Totale 190.954
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.203 0 0 0 0 0 188 122 196 153 208 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20254.938 53 552 258 780 271 179 297 456 775 249 280 788
2025/20263.600 611 360 607 810 602 610 0 0 0 0 0 0
Totale 36.127