PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
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Continente #
EU - Europa 16.371
NA - Nord America 15.238
AS - Asia 10.659
SA - Sud America 721
AF - Africa 231
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 13
Totale 43.248
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Nazione #
US - Stati Uniti d'America 15.022
IT - Italia 3.649
SG - Singapore 3.189
DE - Germania 2.912
GB - Regno Unito 2.895
CN - Cina 2.618
FR - Francia 2.559
VN - Vietnam 2.528
RU - Federazione Russa 1.706
BR - Brasile 586
UA - Ucraina 549
NL - Olanda 489
HK - Hong Kong 454
KR - Corea 425
TR - Turchia 390
IE - Irlanda 389
IN - India 293
CH - Svizzera 208
AT - Austria 201
FI - Finlandia 191
CA - Canada 163
BE - Belgio 147
SE - Svezia 144
JP - Giappone 126
SN - Senegal 110
JO - Giordania 81
PH - Filippine 79
TW - Taiwan 76
ID - Indonesia 75
TH - Thailandia 75
IQ - Iraq 57
ES - Italia 51
AR - Argentina 45
BG - Bulgaria 42
RO - Romania 38
BD - Bangladesh 37
EU - Europa 29
MX - Messico 28
PK - Pakistan 27
PL - Polonia 25
ZA - Sudafrica 24
IL - Israele 22
CL - Cile 20
IR - Iran 20
MA - Marocco 20
GH - Ghana 19
CZ - Repubblica Ceca 18
EC - Ecuador 18
EE - Estonia 17
MY - Malesia 17
EG - Egitto 15
SA - Arabia Saudita 15
VE - Venezuela 15
CO - Colombia 14
AU - Australia 13
DK - Danimarca 13
UZ - Uzbekistan 13
PT - Portogallo 12
AL - Albania 11
AE - Emirati Arabi Uniti 10
TN - Tunisia 10
KZ - Kazakistan 9
AZ - Azerbaigian 8
GR - Grecia 8
LT - Lituania 8
PE - Perù 8
BY - Bielorussia 7
DZ - Algeria 7
KE - Kenya 7
OM - Oman 6
PY - Paraguay 6
CY - Cipro 5
LB - Libano 5
LV - Lettonia 5
NP - Nepal 5
SY - Repubblica araba siriana 5
AM - Armenia 4
AP - ???statistics.table.value.countryCode.AP??? 4
CR - Costa Rica 4
NG - Nigeria 4
NO - Norvegia 4
QA - Qatar 4
UY - Uruguay 4
XK - ???statistics.table.value.countryCode.XK??? 4
BB - Barbados 3
BH - Bahrain 3
GY - Guiana 3
HR - Croazia 3
LK - Sri Lanka 3
PA - Panama 3
PR - Porto Rico 3
SI - Slovenia 3
AO - Angola 2
BO - Bolivia 2
CI - Costa d'Avorio 2
DO - Repubblica Dominicana 2
ET - Etiopia 2
HN - Honduras 2
JM - Giamaica 2
KG - Kirghizistan 2
Totale 43.215
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Città #
Ashburn 3.262
Southend 2.574
Singapore 1.796
Seattle 1.457
Turin 1.138
Fairfield 929
San Jose 765
Chandler 696
Ho Chi Minh City 677
Hanoi 592
Torino 504
Beijing 494
Woodbridge 484
Boardman 467
Houston 438
Princeton 420
Ann Arbor 391
Dublin 372
Wilmington 357
Santa Clara 353
Hong Kong 338
Cambridge 332
Hangzhou 323
Jacksonville 281
Moscow 277
Berlin 250
Hefei 230
Dallas 222
Seoul 198
Izmir 194
Los Angeles 180
Chicago 179
Milan 177
Bern 172
San Ramon 165
Frankfurt 158
Lauterbourg 156
Herkenbosch 144
Tongling 143
Helsinki 141
Istanbul 133
Brussels 128
Vienna 128
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Council Bluffs 114
Da Nang 111
Shanghai 110
Rotterdam 109
Buffalo 104
Zhengzhou 100
Haiphong 98
Des Moines 93
Nuremberg 91
Zaporozhye 78
Mountain View 77
Putian 75
Baltimore 70
Rome 69
Groningen 68
Pennsylvania Furnace 66
Bologna 65
New York 62
Frankfurt am Main 61
San Francisco 60
Jakarta 59
Monopoli 55
Ottawa 54
Redwood City 54
Lecce 52
São Paulo 51
Guangzhou 48
Overberg 47
Tokyo 46
The Dalles 44
Toronto 43
Las Vegas 41
Munich 40
Amsterdam 39
Dearborn 39
Sofia 37
Fremont 36
Hải Dương 35
San Diego 34
London 33
Bangkok 31
Columbus 31
Malatya 31
North Bergen 31
Padua 30
Porto Alegre 30
Can Tho 25
Falls Church 25
Nha Trang 25
Norwalk 25
Biên Hòa 24
Orem 24
Lappeenranta 23
Paris 23
Totale 26.130
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Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 742
On-chip Thermal Modeling Based on SPICE Simulation 719
Modeling of thermally induced skew variations in clock distribution network 677
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 643
An on-chip all-digital PV-monitoring architecture for digital IPs 633
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 610
Aging Effects of Leakage Optimizations for Caches 581
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 565
Buffering of frequent accesses for reduced cache aging 510
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 489
Partitioned cache architectures for reduced NBTI-induced aging 481
Power-Gating: More Than Leakage Savings 471
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 460
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 456
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 451
The Human Brain Project and Neuromorphic computing 434
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 430
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 412
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 407
An integrated thermal estimation framework for industrial embedded platforms 403
Design Techniques and Architectures for Low-Leakage SRAMs 401
An integrated thermal estimation framework for industrial embedded platforms. 397
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 393
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 391
Delay model for reconfigurable logic gates based on graphene PN-junctions 387
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 385
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 379
Characterizing the activity factor in NBTI aging models for embedded cores 378
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 378
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 376
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 372
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 371
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 370
Energy-optimal caches with guaranteed lifetime 369
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 366
Exploration of different implementation styles for graphene-based reconfigurable gates 364
Dual-Vt Assignment Policies in ITD-Aware Synthesis 362
NBTI effects on tree-like clock distribution networks 362
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 361
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 359
Modeling of Physical Defects in PN-Junction Based Graphene Devices 358
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 357
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 349
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 348
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 347
Power Modeling and Characterization of Graphene-Based Logic Gates 344
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 343
IR-Drop Analysis of Graphene-Based Power Distribution Networks 341
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 335
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 335
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 334
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 332
NBTI-Aware Clustered Power Gating 328
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 328
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 327
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 321
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 314
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 310
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 310
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 307
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 306
Placement-aware clustering for integrated clock and power gating 305
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 304
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 303
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 300
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 300
Enabling concurrent clock and power gating in an industrial design flow 299
Design Techniques for NBTI-Tolerant Power-Gating Architectures 298
Post-placement temperature reduction techniques 298
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 298
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 298
ACME: An energy-efficient approximate bus encoding for I2C 297
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 297
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 296
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 290
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 284
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 280
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 273
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 270
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 269
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 258
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 258
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 254
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference 252
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 251
Activation-kernel extraction through machine learning 242
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 240
Monocular Depth Perception on Microcontrollers for Edge Applications 239
All-digital embedded meters for on-line power estimation 235
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 234
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 234
Power and Aging Characterization of Digital FIR Filters Architectures 232
Enabling monocular depth perception at the very edge 230
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 227
Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption 226
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 226
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 226
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers 220
SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing 219
Multiplication by Inference using Classification Trees: A Case-Study Analysis 219
Totale 35.350
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Categoria #
all - tutte 106.014
article - articoli 28.460
book - libri 0
conference - conferenze 73.668
curatela - curatele 446
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.440
Totale 212.028
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021336 0 0 0 0 0 0 0 0 0 0 130 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20254.938 53 552 258 780 271 179 297 456 775 249 280 788
2025/202611.093 611 360 607 810 602 652 1.717 1.065 2.814 1.670 185 0
Totale 43.620