PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
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Continente #
EU - Europa 16.495
NA - Nord America 15.601
AS - Asia 10.739
SA - Sud America 722
AF - Africa 231
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 13
Totale 43.816
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Nazione #
US - Stati Uniti d'America 15.357
IT - Italia 3.766
SG - Singapore 3.198
DE - Germania 2.912
GB - Regno Unito 2.896
CN - Cina 2.624
FR - Francia 2.559
VN - Vietnam 2.528
RU - Federazione Russa 1.706
BR - Brasile 586
UA - Ucraina 549
NL - Olanda 489
HK - Hong Kong 456
KR - Corea 426
TR - Turchia 390
IE - Irlanda 389
IN - India 294
CH - Svizzera 209
AT - Austria 201
FI - Finlandia 191
CA - Canada 184
BE - Belgio 147
SE - Svezia 144
JP - Giappone 128
SN - Senegal 110
BD - Bangladesh 94
JO - Giordania 81
PH - Filippine 79
TW - Taiwan 76
ID - Indonesia 75
TH - Thailandia 75
IQ - Iraq 57
ES - Italia 53
AR - Argentina 45
BG - Bulgaria 42
RO - Romania 38
EU - Europa 29
MX - Messico 28
PK - Pakistan 28
PL - Polonia 25
ZA - Sudafrica 24
IL - Israele 22
CL - Cile 21
IR - Iran 20
MA - Marocco 20
GH - Ghana 19
CZ - Repubblica Ceca 18
EC - Ecuador 18
EE - Estonia 17
MY - Malesia 17
EG - Egitto 15
SA - Arabia Saudita 15
VE - Venezuela 15
CO - Colombia 14
UZ - Uzbekistan 14
AU - Australia 13
DK - Danimarca 13
PT - Portogallo 12
AL - Albania 11
AE - Emirati Arabi Uniti 10
TN - Tunisia 10
KZ - Kazakistan 9
AZ - Azerbaigian 8
GR - Grecia 8
LT - Lituania 8
PE - Perù 8
BY - Bielorussia 7
DZ - Algeria 7
KE - Kenya 7
OM - Oman 6
PY - Paraguay 6
CR - Costa Rica 5
CY - Cipro 5
LB - Libano 5
LV - Lettonia 5
NP - Nepal 5
SY - Repubblica araba siriana 5
TT - Trinidad e Tobago 5
AM - Armenia 4
AP - ???statistics.table.value.countryCode.AP??? 4
NG - Nigeria 4
NO - Norvegia 4
QA - Qatar 4
UY - Uruguay 4
XK - ???statistics.table.value.countryCode.XK??? 4
BB - Barbados 3
BH - Bahrain 3
GY - Guiana 3
HR - Croazia 3
IS - Islanda 3
JM - Giamaica 3
LK - Sri Lanka 3
PA - Panama 3
PR - Porto Rico 3
SI - Slovenia 3
AO - Angola 2
BO - Bolivia 2
CI - Costa d'Avorio 2
DO - Repubblica Dominicana 2
ET - Etiopia 2
Totale 43.779
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Città #
Ashburn 3.280
Southend 2.574
Singapore 1.797
Seattle 1.458
Turin 1.140
Fairfield 929
San Jose 875
Chandler 696
Ho Chi Minh City 677
Hanoi 592
Torino 504
Beijing 494
Woodbridge 484
Boardman 478
Houston 440
Princeton 420
Ann Arbor 391
Dublin 372
Santa Clara 362
Wilmington 357
Hong Kong 340
Cambridge 332
Hangzhou 323
Jacksonville 282
Moscow 277
Berlin 250
Hefei 230
Dallas 228
Milan 206
Seoul 198
Izmir 194
Los Angeles 186
Chicago 180
Bern 172
San Ramon 165
Frankfurt 158
Lauterbourg 156
Herkenbosch 144
Tongling 143
Helsinki 141
Council Bluffs 135
Istanbul 133
Brussels 128
Vienna 128
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Shanghai 112
Da Nang 111
Buffalo 110
Rotterdam 109
Zhengzhou 100
Haiphong 98
Des Moines 93
Nuremberg 91
New York 85
Zaporozhye 78
Mountain View 77
Putian 75
Rome 75
Baltimore 70
Groningen 68
Bologna 66
Pennsylvania Furnace 66
Frankfurt am Main 61
San Francisco 60
Jakarta 59
Monopoli 55
Ottawa 55
Redwood City 55
Lecce 52
São Paulo 51
Guangzhou 48
The Dalles 48
Toronto 48
Overberg 47
Tokyo 47
Las Vegas 41
Munich 40
Amsterdam 39
Dearborn 39
Sofia 37
Fremont 36
Hải Dương 35
London 34
San Diego 34
Columbus 32
Bangkok 31
Malatya 31
North Bergen 31
Padua 30
Porto Alegre 30
Can Tho 25
Falls Church 25
Nha Trang 25
Norwalk 25
Orem 25
Biên Hòa 24
Lappeenranta 23
Montreal 23
Totale 26.403
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Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 744
On-chip Thermal Modeling Based on SPICE Simulation 723
Modeling of thermally induced skew variations in clock distribution network 679
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 646
An on-chip all-digital PV-monitoring architecture for digital IPs 636
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 618
Aging Effects of Leakage Optimizations for Caches 588
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 578
Buffering of frequent accesses for reduced cache aging 515
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 497
Partitioned cache architectures for reduced NBTI-induced aging 486
Power-Gating: More Than Leakage Savings 475
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 461
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 460
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 452
The Human Brain Project and Neuromorphic computing 435
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 431
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 417
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 409
An integrated thermal estimation framework for industrial embedded platforms 406
Design Techniques and Architectures for Low-Leakage SRAMs 404
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 399
An integrated thermal estimation framework for industrial embedded platforms. 398
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 395
Delay model for reconfigurable logic gates based on graphene PN-junctions 388
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 387
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 382
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 380
Characterizing the activity factor in NBTI aging models for embedded cores 379
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 378
Dual-Vt Assignment Policies in ITD-Aware Synthesis 377
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 374
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 373
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 372
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 370
Energy-optimal caches with guaranteed lifetime 369
Exploration of different implementation styles for graphene-based reconfigurable gates 366
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 362
NBTI effects on tree-like clock distribution networks 362
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 361
Modeling of Physical Defects in PN-Junction Based Graphene Devices 360
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 357
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 357
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 351
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 349
Power Modeling and Characterization of Graphene-Based Logic Gates 345
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 345
IR-Drop Analysis of Graphene-Based Power Distribution Networks 342
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 338
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 337
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 337
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 332
NBTI-Aware Clustered Power Gating 329
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 329
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 328
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 326
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 316
ACME: An energy-efficient approximate bus encoding for I2C 316
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 312
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 311
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 309
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 308
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 306
Placement-aware clustering for integrated clock and power gating 306
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 306
Enabling concurrent clock and power gating in an industrial design flow 303
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 302
Post-placement temperature reduction techniques 302
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 301
Design Techniques for NBTI-Tolerant Power-Gating Architectures 300
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 300
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 300
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 298
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 297
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 292
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 284
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 283
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 274
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 272
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 270
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 260
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 260
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 259
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference 259
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 258
Monocular Depth Perception on Microcontrollers for Edge Applications 250
Activation-kernel extraction through machine learning 243
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 242
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 237
Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption 236
All-digital embedded meters for on-line power estimation 236
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 236
Power and Aging Characterization of Digital FIR Filters Architectures 233
Enabling monocular depth perception at the very edge 233
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 232
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 230
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 229
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers 226
SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing 223
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets 222
Totale 35.666
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Categoria #
all - tutte 109.259
article - articoli 29.483
book - libri 0
conference - conferenze 75.749
curatela - curatele 458
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.569
Totale 218.518
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021206 0 0 0 0 0 0 0 0 0 0 0 206
2021/20221.882 106 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20254.938 53 552 258 780 271 179 297 456 775 249 280 788
2025/202611.664 611 360 607 810 602 652 1.717 1.065 2.814 1.670 427 329
Totale 44.191