PORTO @ Archivio Istituzionale della Ricerca

CALIMERA, ANDREA
 Distribuzione geografica
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Continente #
EU - Europa 16.647
NA - Nord America 16.098
AS - Asia 10.834
SA - Sud America 758
Continente sconosciuto - Info sul continente non disponibili 388
AF - Africa 231
OC - Oceania 15
Totale 44.971
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Nazione #
US - Stati Uniti d'America 15.791
IT - Italia 3.871
SG - Singapore 3.233
DE - Germania 2.914
GB - Regno Unito 2.896
CN - Cina 2.627
FR - Francia 2.561
VN - Vietnam 2.529
RU - Federazione Russa 1.706
BR - Brasile 606
UA - Ucraina 550
NL - Olanda 489
HK - Hong Kong 457
KR - Corea 426
IE - Irlanda 390
TR - Turchia 390
IN - India 295
CH - Svizzera 211
AT - Austria 201
CA - Canada 201
FI - Finlandia 191
SE - Svezia 175
BE - Belgio 147
BD - Bangladesh 136
JP - Giappone 129
SN - Senegal 110
PH - Filippine 86
JO - Giordania 81
TW - Taiwan 77
ID - Indonesia 75
TH - Thailandia 75
IQ - Iraq 57
ES - Italia 55
AR - Argentina 49
BG - Bulgaria 42
RO - Romania 39
MX - Messico 32
EU - Europa 29
PK - Pakistan 29
PL - Polonia 26
ZA - Sudafrica 24
CL - Cile 23
IL - Israele 22
CO - Colombia 21
EC - Ecuador 20
IR - Iran 20
MA - Marocco 20
CZ - Repubblica Ceca 19
GH - Ghana 19
JM - Giamaica 18
MY - Malesia 18
EE - Estonia 17
SA - Arabia Saudita 16
VE - Venezuela 16
CR - Costa Rica 15
EG - Egitto 15
UZ - Uzbekistan 14
AU - Australia 13
DK - Danimarca 13
AL - Albania 12
PT - Portogallo 12
AE - Emirati Arabi Uniti 10
TN - Tunisia 10
KZ - Kazakistan 9
AZ - Azerbaigian 8
GR - Grecia 8
HN - Honduras 8
LT - Lituania 8
PE - Perù 8
BY - Bielorussia 7
DZ - Algeria 7
KE - Kenya 7
TT - Trinidad e Tobago 7
OM - Oman 6
PY - Paraguay 6
CY - Cipro 5
LB - Libano 5
LV - Lettonia 5
NP - Nepal 5
SY - Repubblica araba siriana 5
AM - Armenia 4
AP - ???statistics.table.value.countryCode.AP??? 4
BB - Barbados 4
NG - Nigeria 4
NI - Nicaragua 4
NO - Norvegia 4
PR - Porto Rico 4
QA - Qatar 4
SV - El Salvador 4
UY - Uruguay 4
XK - ???statistics.table.value.countryCode.XK??? 4
BH - Bahrain 3
GY - Guiana 3
HR - Croazia 3
IS - Islanda 3
LK - Sri Lanka 3
PA - Panama 3
SI - Slovenia 3
SK - Slovacchia (Repubblica Slovacca) 3
AO - Angola 2
Totale 44.555
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Città #
Ashburn 3.339
Southend 2.574
Singapore 1.804
Seattle 1.459
Turin 1.144
Fairfield 929
San Jose 917
Chandler 696
Ho Chi Minh City 677
Hanoi 592
Torino 504
Beijing 496
Woodbridge 484
Boardman 478
Houston 443
Princeton 420
Ann Arbor 391
Santa Clara 379
Dublin 372
Wilmington 357
Hong Kong 341
Cambridge 332
Hangzhou 323
Jacksonville 284
Moscow 277
Berlin 250
Milan 247
Dallas 235
Hefei 230
Council Bluffs 212
Seoul 198
Izmir 194
Los Angeles 192
Chicago 187
Bern 172
San Ramon 165
Frankfurt 158
Lauterbourg 156
Herkenbosch 144
Tongling 143
Helsinki 141
Istanbul 133
Vienna 129
Brussels 128
Bremen 126
San Donato Milanese 122
Saint Petersburg 121
Buffalo 112
Shanghai 112
Da Nang 111
Rotterdam 109
Zhengzhou 100
Haiphong 98
Rome 95
Des Moines 93
New York 92
Nuremberg 91
Zaporozhye 78
Mountain View 77
Putian 75
Baltimore 71
Groningen 68
Bologna 67
Pennsylvania Furnace 66
Frankfurt am Main 63
San Francisco 62
Jakarta 59
Monopoli 55
Ottawa 55
Redwood City 55
São Paulo 54
Lecce 52
The Dalles 52
Toronto 51
Guangzhou 48
Tokyo 48
Overberg 47
Las Vegas 42
Munich 40
Amsterdam 39
Dearborn 39
Sofia 37
Fremont 36
Hải Dương 36
Columbus 35
London 34
San Diego 34
Bangkok 31
Malatya 31
North Bergen 31
Padua 31
Porto Alegre 30
Washington 27
Can Tho 25
Falls Church 25
Nha Trang 25
Norwalk 25
Orem 25
Biên Hòa 24
Brooklyn 24
Totale 26.737
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Nome #
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy 745
On-chip Thermal Modeling Based on SPICE Simulation 728
Modeling of thermally induced skew variations in clock distribution network 697
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating 664
An on-chip all-digital PV-monitoring architecture for digital IPs 653
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering 627
Aging Effects of Leakage Optimizations for Caches 601
Ultra-low power circuits using graphene p-n junctions and adiabatic computing 585
Buffering of frequent accesses for reduced cache aging 525
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs 505
Partitioned cache architectures for reduced NBTI-induced aging 495
Power-Gating: More Than Leakage Savings 487
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture 463
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization 462
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems 461
The Human Brain Project and Neuromorphic computing 437
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits 432
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions 420
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits 416
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks 413
An integrated thermal estimation framework for industrial embedded platforms 409
Design Techniques and Architectures for Low-Leakage SRAMs 407
An integrated thermal estimation framework for industrial embedded platforms. 402
Dual-Vt Assignment Policies in ITD-Aware Synthesis 398
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits 398
Delay model for reconfigurable logic gates based on graphene PN-junctions 393
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation 391
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 385
Efficient Deep Learning Models for Privacy-preserving People Counting on Low-resolution Infrared Arrays 383
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing 383
Characterizing the activity factor in NBTI aging models for embedded cores 382
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies 379
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology 379
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs 376
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 376
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping 373
Energy-optimal caches with guaranteed lifetime 371
Exploration of different implementation styles for graphene-based reconfigurable gates 371
Thermal-Aware Design Techniques for Nanometer CMOS Circuits 365
NBTI effects on tree-like clock distribution networks 365
Modeling of Physical Defects in PN-Junction Based Graphene Devices 365
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating 364
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints 360
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture 353
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits 351
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits 351
Power Modeling and Characterization of Graphene-Based Logic Gates 346
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits 346
IR-Drop Analysis of Graphene-Based Power Distribution Networks 345
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs 341
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future 339
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits 337
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices 336
NBTI-Aware Clustered Power Gating 335
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating 334
Automatic Layer Freezing for Communication Efficiency in Cross-Device Federated Learning 329
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches 320
ACME: An energy-efficient approximate bus encoding for I2C 319
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates 316
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation 314
Manufacturing as a Data-Driven Practice: Methodologies, Technologies, and Tools 314
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints 312
Placement-aware clustering for integrated clock and power gating 311
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems 310
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence 310
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs 306
Post-placement temperature reduction techniques 304
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization 304
Enabling concurrent clock and power gating in an industrial design flow 304
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits 304
Design Techniques for NBTI-Tolerant Power-Gating Architectures 302
Temperature-Insensitive Synthesis Using Multi-Vt Libraries 302
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits 302
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells 299
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization 295
On-Chip PV Tracking Through an All-Digital Monitoring Architecture 286
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling 283
Reducing the Energy Consumption of sEMG-Based Gesture Recognition at the Edge Using Transformers and Dynamic Inference 279
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets 277
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs 275
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis 273
Energy-Quality Scalable Monocular Depth Estimation on Low-Power CPUs 271
Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS 264
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems 261
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models 260
Monocular Depth Perception on Microcontrollers for Edge Applications 260
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches 245
Activation-kernel extraction through machine learning 245
Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption 242
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS 241
Enabling monocular depth perception at the very edge 240
On the Efficiency of Sparse-Tiled Tensor Graph Processing for Low Memory Usage 240
All-digital embedded meters for on-line power estimation 239
Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers 238
Fast and Accurate Inference on Microcontrollers with Boosted Cooperative Convolutional Neural Networks (BC-Net) 236
Power and Aging Characterization of Digital FIR Filters Architectures 233
TVFS: Topology Voltage Frequency Scaling for Reliable Embedded ConvNets 233
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets 231
Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching 230
SMART-IC: Smart Monitoring and Production Optimization for Zero-waste Semiconductor Manufacturing 227
Totale 36.191
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Categoria #
all - tutte 112.987
article - articoli 30.721
book - libri 0
conference - conferenze 78.083
curatela - curatele 475
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.708
Totale 225.974
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/20221.776 0 104 189 60 83 194 86 80 46 192 352 390
2022/20232.787 218 410 114 246 381 380 253 152 269 55 98 211
2023/20241.082 43 87 149 84 102 110 39 48 16 86 117 201
2024/20254.938 53 552 258 780 271 179 297 456 775 249 280 788
2025/202611.891 611 360 607 810 602 652 1.717 1.065 2.814 1.670 427 556
2026/2027553 333 220 0 0 0 0 0 0 0 0 0 0
Totale 44.971