Placement-aware clustering for integrated clock and power gating

Clock-gating and power-gating are the most widely used solutions for reducing dynamic and static power. They can be potentially integrated so that clock-gating conditions can be used to control the power-gating circuitry thus also reducing static power. This integration becomes however difficult when applied in an industrial design flow. Even if both clock and power- gating are supported by most commercial synthesis tools, their combined implementation requires some flexibility in the back-end tools that is not currently available. This paper propose a layout-oriented synthesis flow which successfully integrates the two techniques by bridging previous efforts in that direction by proposing an efficient clustering algorithm that minimizes the area and the performance overhead while achieving a significant leakage reduction. The entire flow and the algorithm have been tested on a set of industrial designs mapped onto a commercial, 65 nm CMOS technology library.