Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flows.

Modeling of thermally induced skew variations in clock distribution network / Sassone, Alessandro; Liu, Wei; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - (2011), pp. 1-6. ((Intervento presentato al convegno 17th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2011 tenutosi a Paris (FRA) nel 27-29 Sept. 2011.

Modeling of thermally induced skew variations in clock distribution network

SASSONE, ALESSANDRO;LIU, WEI;CALIMERA, ANDREA;MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO
2011

Abstract

Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flows.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2471379
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